公开(公告)号：US07823098B1

公开(公告)日：2010-10-26

申请号：US11590581

申请日：2006-10-31

申请人： Cho W. Moon ,  Puneet Gupta ,  Paul J. Donehue ,  Andrew B. Kahng

发明人： Cho W. Moon ,  Puneet Gupta ,  Paul J. Donehue ,  Andrew B. Kahng

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method of designing a digital circuit is described, so that it is likely to pass a signoff time test. The method begins with the running of a basic static time test on a partially developed version of the digital circuit, next a signoff time test is run for the partially developed version of the digital system. The differences between the results of the basic static time test and the signoff time test are noted and the prospective basic static time test passing conditions are altered so that if a similar system passes the basic static time test with the altered passing conditions it will be more likely to pass the signoff time test. Then, the partially developed version of the digital system is altered to yield a second partially developed version and the first static time test is run, with the altered passing conditions on the second partially developed version.

摘要翻译： 描述了一种设计数字电路的方法，从而可能通过签发时间测试。 该方法开始于在数字电路的部分开发版本上运行基本静态时间测试，接下来对数字系统的部分开发版本进行签发时间测试。 注意基本静态时间测试和签发时间测试的结果之间的差异，并改变预期的基本静态时间测试通过条件，以便如果类似的系统通过基本的静态时间测试与改变的通过条件，将会更多 可能通过签退时间测试。 然后，数字系统的部分开发版本被改变以产生第二部分开发的版本，并且运行第一静态时间测试，在第二部分开发版本上改变了通过条件。