公开(公告)号：US5353281A

公开(公告)日：1994-10-04

申请号：US889952

申请日：1992-05-29

申请人： Hiroshi Kuwahara ,  Kazuhiro Suzuki ,  Toshikazu Sasa ,  Kenzo Urabe ,  Arata Nakagoshi ,  Hideya Suzuki ,  Yohichi Ogawa ,  Tsuneo Furuya ,  Yoshinobu Yamamoto

发明人： Hiroshi Kuwahara ,  Kazuhiro Suzuki ,  Toshikazu Sasa ,  Kenzo Urabe ,  Arata Nakagoshi ,  Hideya Suzuki ,  Yohichi Ogawa ,  Tsuneo Furuya ,  Yoshinobu Yamamoto

IPC分类号： H04Q7/22 ,  H04Q7/28 ,  H04Q11/04

CPC分类号： H04Q11/04

摘要： An intermittenceless switching system includes two speech path memories having sufficient capacity to store a single frame of data having a plurality of time slots. The incoming data is stored in one memory, while the outgoing data is read from the other memory. A control circuit continuously alternates the read/write functions between the two memories. A control memory is used to store switch control information. The system includes a buffer memory that is present between a data processor and the control memory to prevent switch operation during data transmission. The system also includes a monitoring circuit for detecting an indication bit signifying the presence or absence of data in the time slot.

摘要翻译： 无间歇切换系统包括具有足够的容量来存储具有多个时隙的单个数据帧的两个语音路径存储器。 输入数据存储在一个存储器中，而从其他存储器读取输出数据。 控制电路在两个存储器之间连续交替读/写功能。 控制存储器用于存储开关控制信息。 该系统包括存在于数据处理器和控制存储器之间的缓冲存储器，以防止在数据传输期间的开关操作。 该系统还包括用于检测表示时隙中是否存在数据的指示位的监视电路。