利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

28 条记录 (耗时 0.018 秒)

    Using selectable in-line inverters to reduce the number of inverters in a semiconductor design
    1.
    发明授权
    Using selectable in-line inverters to reduce the number of inverters in a semiconductor design 有权
    使用可选择的在线逆变器来减少半导体设计中的逆变器数量

    公开(公告)号：US07930670B2

    公开(公告)日：2011-04-19

    申请号：US12432494

    申请日：2009-04-29

    申请人： William D. Cox

    发明人： William D. Cox

    IPC分类号： G06F17/50

    CPC分类号： H03K19/1733 ,  H03K19/1735 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17796

    摘要： Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.

    摘要翻译： 逻辑阵列器件具有复杂的宏单元结构和便于使用它们的方法。 包括逻辑单元和可编程金属阵列的半导体器件包括预先布线的栅极结构，其中输入和/或输出可用于可编程金属中的布线，可能是混合工艺的一部分。 该器件还可以包括可选择的在线逆变器，其可以与逻辑输入共享输入/输出轨道。 气泡推动算法可以利用可选择的在线逆变器来减少设计中的逆变器数量。 在一些实施例中，嵌入式时钟线对于多个逻辑单元是公用的。 时钟线在时钟单元中终止，时钟单元可以包括测试逻辑，从而形成时钟组。 可以通过具有可编程连接的电源轨迹提供对电池或电池组断电的灵活性。

    Configurable integrated circuit capacitor array using via mask layers
    3.
    发明授权
    Configurable integrated circuit capacitor array using via mask layers 有权
    可配置的集成电路电容阵列使用通孔掩模层

    公开(公告)号：US07335966B2

    公开(公告)日：2008-02-26

    申请号：US10906527

    申请日：2005-02-23

    申请人： David Ihme ,  James C. Kemerling ,  William D. Cox

    发明人： David Ihme ,  James C. Kemerling ,  William D. Cox

    IPC分类号： H01L29/00

    CPC分类号： H01G4/385 ,  H01L27/0805 ,  H01L2924/14 ,  H01L2924/00

    摘要： A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.

    摘要翻译： 具有多个层的半导体器件和包括多个单独的电容器的电容器阵列。 半导体器件中的多个层中的至少一个可以是被配置为确定电容器阵列中的多个单独电容器的连接和电容的通孔层。 半导体器件可以包括设置在器件内的金属结构，以为电容器阵列中的多个独立电容器中的至少一个提供电磁屏蔽。

    Field programmable antifuse device and programming method therefor
    4.
    发明授权
    Field programmable antifuse device and programming method therefor 失效
    现场可编程反熔丝装置及其编程方法

    公开(公告)号：US5469077A

    公开(公告)日：1995-11-21

    申请号：US263985

    申请日：1994-06-22

    申请人： William D. Cox

    发明人： William D. Cox

    IPC分类号： G11C17/16 ,  H03K19/177

    CPC分类号： H03K19/17748 ,  G11C17/16 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

    摘要： A method for reducing the resistance of a programing path through a programmable antifuse from a programming voltage to ground. A previously programmed helper antifuse connected somewhere along a two branch programming path is connected to either the programming voltage or to ground. As a result, a three branch programming path is established from the programming voltage to the antifuse to be programmed and from the antifuse to be programmed to ground. By adding the third branch to the programming path, the resistance of the programming path is reduced, thereby allowing a higher voltage to be dropped across the antifuse to be programmed during programming and thereby allowing increased current flow through the antifuse to be programmed during programming. In another embodiment, two or more helper antifuses are used to establish a four or more branch programming path having a still lower resistance from the programming voltage to ground. In yet another embodiment, the programming of antifuses occurs in two steps. First, multiple antifuses are partially programmed separately. Second, these partially programmed antifuses are connected together in series so that a programming current can flow through all of the partially programmed antifuses at once to complete programming of the multiple antifuses.

    摘要翻译： 一种通过可编程反熔丝将编程路径的电阻从编程电压降低到地的方法。 连接在两个分支编程路径的某处的先前编程的辅助反熔丝连接到编程电压或接地。 结果，从编程电压到要编程的反熔丝和从反熔丝编程到地的三个分支编程路径被建立。 通过将第三分支添加到编程路径中，编程路径的电阻降低，从而允许在编程期间在待编程的反熔丝之间降低更高的电压，从而允许在编程期间通过反熔丝增加的电流流动被编程。 在另一个实施例中，使用两个或更多个辅助反熔丝来建立四个或更多个分支编程路径，其具有从编程电压到地的更低的电阻。 在另一个实施例中，反熔丝的编程分两步进行。 首先，单独部分编程多个反熔丝。 第二，这些部分编程的反熔丝串联连接在一起，使得编程电流可以一次流过所有部分编程的反熔丝，以完成对多个反熔丝的编程。

    LOGIC ARRAY DEVICES HAVING COMPLEX MACRO-CELL ARCHITECTURE AND METHODS FACILITATING USE OF SAME
    6.
    发明申请
    LOGIC ARRAY DEVICES HAVING COMPLEX MACRO-CELL ARCHITECTURE AND METHODS FACILITATING USE OF SAME 有权
    具有复杂宏小结构的逻辑阵列设备及其使用方法

    公开(公告)号：US20090210848A1

    公开(公告)日：2009-08-20

    申请号：US12432494

    申请日：2009-04-29

    申请人： William D. COX

    发明人： William D. COX

    IPC分类号： G06F17/50

    CPC分类号： H03K19/1733 ,  H03K19/1735 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17796

    摘要： Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.

    摘要翻译： 逻辑阵列器件具有复杂的宏单元结构和便于使用它们的方法。 包括逻辑单元和可编程金属阵列的半导体器件包括预先布线的栅极结构，其中输入和/或输出可用于可编程金属中的布线，可能是混合工艺的一部分。 该器件还可以包括可选择的在线逆变器，其可以与逻辑输入共享输入/输出轨道。 气泡推动算法可以利用可选择的在线逆变器来减少设计中的逆变器数量。 在一些实施例中，嵌入式时钟线对于多个逻辑单元是公用的。 时钟线在时钟单元中终止，时钟单元可以包括测试逻辑，从而形成时钟组。 可以通过具有可编程连接的电源轨迹提供对电池或电池组断电的灵活性。

    VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE
    7.
    发明申请
    VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE 有权
    通过半导体器件中模拟电路自定义的可配置架构

    公开(公告)号：US20090032968A1

    公开(公告)日：2009-02-05

    申请号：US12246802

    申请日：2008-10-07

    申请人： James C. Kemerling ,  David Ihme ,  William D. Cox

    发明人： James C. Kemerling ,  David Ihme ,  William D. Cox

    IPC分类号： H01L23/522

    CPC分类号： H03K19/17736 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17748 ,  H03K19/17796 ,  H01L2924/00

    摘要： A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

    摘要翻译： 具有多个层的半导体器件和布置在瓦片中的多个电路元件。 半导体器件中的多个层中的至少一个可以是经配置以确定多个电路元件的连接的通孔层。 半导体器件可以包括具有设置成互连多个电路元件的多个金属层的互连被子。 多个电路元件可以是模拟电路元件和/或数字电路元件。 瓦片可以是形成混合信号结构阵列的模拟瓦片和数字瓦片。

    Creating high-drive logic devices from standard gates with minimal use of custom masks
    8.
    发明授权
    Creating high-drive logic devices from standard gates with minimal use of custom masks 有权
    从标准门创建高驱动逻辑器件，最少使用自定义掩码

    公开(公告)号：US07378874B2

    公开(公告)日：2008-05-27

    申请号：US11469189

    申请日：2006-08-31

    申请人： Bhaskar Bharath ,  William D. Cox

    发明人： Bhaskar Bharath ,  William D. Cox

    IPC分类号： H03K19/173

    CPC分类号： H03K19/177

    摘要： Logic cells in an application-specific integrated circuit (ASIC) emulating standard gate sizing by duplicating elements within a single standard gate where logical high-drive gates are synthesized and converted to parallel elements as a post-process. The drive characteristics of the logical gates are retained during the conversion to the physical gate equivalents in the standard cell architecture. The logic cells in the device may include, for example, at least two two-input multiplexers.

    摘要翻译： 应用专用集成电路（ASIC）中的逻辑单元通过在逻辑高驱动门合成并转换为并行元件作为后处理的单个标准门内复制元件来模拟标准门尺寸。 逻辑门的驱动特性在转换为标准单元体系结构中的物理门当量时被保留。 设备中的逻辑单元可以包括例如至少两个双输入多路复用器。

    Customization of structured ASIC devices using pre-process extraction of routing information
    9.
    发明授权
    Customization of structured ASIC devices using pre-process extraction of routing information 有权
    使用预处理提取路由信息定制结构化ASIC设备

    公开(公告)号：US07334208B1

    公开(公告)日：2008-02-19

    申请号：US10904411

    申请日：2004-11-09

    申请人： William D. Cox

    发明人： William D. Cox

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： Customization of structured ASIC devices using pre-process extraction of routing information. Embodiments of the invention can enable a router that can automatically extract a routing graph for a structured ASIC, where the routing graph represents available routing resources on fixed metal layers. The routing graph can be extracted as a pre-process, and saved in a technology file for later use by the router. Additionally, each unique fixed metal wire type found in the layout can be characterized with a master wire definition, including resistance and capacitance estimates. In some embodiments, a global-routing graph can further be extracted from a detailed routing graph.

    摘要翻译： 使用预处理提取路由信息定制结构化ASIC设备。 本发明的实施例可以使得能够自动提取结构化ASIC的路由图的路由器，其中路由图表示固定金属层上的可用路由资源。 可以将路由图提取为预处理，并保存在技术文件中供路由器稍后使用。 另外，在布局中发现的每个独特的固定金属线类型可以用主导线定义来表征，包括电阻和电容估计。 在一些实施例中，还可以从详细的路由图中提取全局路由图。

    Logic array devices having complex macro-cell architecture and methods facilitating use of same
    10.
    发明授权
    Logic array devices having complex macro-cell architecture and methods facilitating use of same 有权
    逻辑阵列器件具有复杂的宏单元结构和便于使用它们的方法

    公开(公告)号：US07248071B2

    公开(公告)日：2007-07-24

    申请号：US11023860

    申请日：2004-12-28

    申请人： William D. Cox

    发明人： William D. Cox

    IPC分类号： G06F7/38 ,  H03K19/177

    CPC分类号： H03K19/1733 ,  H03K19/1735 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17796

    摘要： Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take advantage of the selectable in-line inverters to reduce the number of inverters in a design. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.

    摘要翻译： 逻辑阵列器件具有复杂的宏单元结构和便于使用它们的方法。 包括逻辑单元和可编程金属阵列的半导体器件包括预先布线的栅极结构，其中输入和/或输出可用于可编程金属中的布线，可能是混合工艺的一部分。 该器件还可以包括可选择的在线逆变器，其可以与逻辑输入共享输入/输出轨道。 气泡推动算法可以利用可选择的在线逆变器来减少设计中的逆变器数量。 在一些实施例中，嵌入式时钟线对于多个逻辑单元是公用的。 时钟线在时钟单元中终止，时钟单元可以包括测试逻辑，从而形成时钟组。 可以通过具有可编程连接的电源轨迹提供对电池或电池组断电的灵活性。