公开(公告)号：US12158806B1

公开(公告)日：2024-12-03

申请号：US18341807

申请日：2023-06-27

Applicant: APPLE INC.

Inventor： Yonathan Tate ,  Amit Pinchas Aylon

IPC: G06F11/10 ,  G06F17/11

Abstract: A controller includes an interface and a processor. The interface communicates with memory cells. The processor reads a Code Word (CW) from the memory cells using read thresholds to produce respective readouts, the read thresholds defining zones, identifies a subgroup of the memory cells associated with zones positioned about a Read Voltage (RV) predetermined between adjacent first and second Programming Voltages (PVs), estimates for each zone, based on the readouts, first and second cumulative counts of the memory cells corresponding to the first and second PVs, models first and second PDFs associated respectively with the memory cells programmed to the first and second PVs, based on the first and second cumulative counts, calculates for the zones respective reliability measures, based on the first and second PDFs, and assigns the reliability measures to bits of the CW, and decodes the CW by applying soft decoding to the assigned reliability measures.