公开(公告)号：US20140089638A1

公开(公告)日：2014-03-27

申请号：US13627884

申请日：2012-09-26

Applicant: APPLE INC.

Inventor： John H. Mylius ,  Gerard R. Williams III ,  James B. Keller ,  Fang Liu ,  Shyam Sundar

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/345 ,  G06F9/384 ,  G06F9/3861 ,  G06F9/3867

Abstract: Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline is configured to merge the plurality of single-destination operations into one or more multi-destination operations. The one or more multi-destination operations may be performed. The first portion of the pipeline may include a decode unit. The second portion of the pipeline may include a map unit, which may in turn include circuitry configured to maintain a list of free architectural registers and a mapping table that maps physical registers to architectural registers. The third portion of the pipeline may comprise a dispatch unit. In some embodiments, this may provide certain advantages such as reduced area and/or power consumption.

Abstract translation: 用于处理指定多个目的地的指令的各种技术。 处理器流水线的第一部分被配置为将多目的地指令分割成多个单目的地操作。 流水线的第二部分被配置为处理多个单目的地操作。 流水线的第三部分被配置为将多个单目的地操作合并成一个或多个多目的地操作。 可以执行一个或多个多目的地操作。 流水线的第一部分可以包括解码单元。 流水线的第二部分可以包括地图单元，其可以依次包括被配置为维护空闲架构寄存器的列表的电路和将物理寄存器映射到架构寄存器的映射表。 管道的第三部分可以包括调度单元。 在一些实施例中，这可以提供某些优点，例如减小面积和/或功率消耗。