公开(公告)号：US20170199738A1

公开(公告)日：2017-07-13

申请号：US14989841

申请日：2016-01-07

Applicant: ARM LIMITED

Inventor： Vladimir VASEKIN ,  Antony John PENTON ,  Chiloda Ashan Senarath PATHIRANE ,  Andrew James Antony LEES

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/384 ,  G06F9/3851

Abstract: Data processing circuitry comprises allocation circuitry to allocate one or more source and destination processor registers, of a set of processor registers each defined by a respective register index, to a processor instruction for use in execution of that processor instruction and to associate, with the processor instruction, information to indicate the register index of the allocated source and destination processor registers; the avocation circuitry being selectively operable to allocate, to a processor instruction, a group of destination processor registers having a subset of their register indices in common and to associate, with the processor instruction, information to indicate the register index of one processor register of the group and identifying information to identify one or more bits of the register index which differ between the processor registers in the allocated group of processor registers.

公开(公告)号：US20170139708A1

公开(公告)日：2017-05-18

申请号：US14941840

申请日：2015-11-16

Applicant: ARM LIMITED

Inventor： Andrew James Antony LEES ,  Ian Michael CAULFIELD ,  Peter Richard GREENHALGH

IPC: G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/3836

Abstract: Data processing circuitry comprises instruction queue circuitry to maintain one or more instruction queues to store fetched instructions; instruction decode circuitry to decode instructions dispatched from the one or more instruction queues, the instruction decode circuitry being configured to allocate one or more processor resources of a set of processor resources to a decoded instruction for use in execution of that decoded instruction; detection circuitry to detect, for an instruction to be dispatched from a given instruction queue, a prediction indicating whether sufficient processor resources are predicted to be available for allocation to that instruction by the instruction decode circuitry; and dispatch circuitry to dispatch an instruction from the given instruction queue to the instruction decode circuitry, the dispatch circuitry being responsive to the detection circuitry to allow deletion of the dispatched instruction from that instruction queue when the prediction indicates that sufficient processor resources are predicted to be available for allocation to that instruction by the instruction decode circuitry.