公开(公告)号：US09478278B1

公开(公告)日：2016-10-25

申请号：US14675687

申请日：2015-03-31

Applicant: ARM Limited

Inventor： Rejeesh Ammanath Vijayan ,  Vikash ,  Pradeep Raj ,  Neelima Gudipati ,  Manish Trivedi ,  Sujit Rout

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16

Abstract: Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

Abstract translation: 本文描述的各种实现涉及用于读写争用的集成电路。 集成电路可以包括具有被配置为接收对应于每个端口的数据信号的多个端口的存储器电路。 集成电路可以包括争用覆盖电路，其基于检测端口之间的读写争用，为每个端口提供争用覆盖信号。 集成电路可以包括具有用于每个端口的多个通行口的写入电路，包括用于每个端口的写通行证和争用通行证。 写入通道可以用来自相应端口的数据信号输入。 可以基于相对的争用覆盖信号，从相对端口输入具有数据信号的争用通行证。

公开(公告)号：US20160293247A1

公开(公告)日：2016-10-06

申请号：US14675687

申请日：2015-03-31

Applicant: ARM Limited

Inventor： Rejeesh Ammanath Vijayan ,  Vikash ,  Pradeep Raj ,  Neelima Gudipati ,  Manish Trivedi ,  Sujit Rout

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16

Abstract: Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

Abstract translation: 本文描述的各种实现涉及用于读写争用的集成电路。 集成电路可以包括具有被配置为接收对应于每个端口的数据信号的多个端口的存储器电路。 集成电路可以包括争用覆盖电路，其基于检测端口之间的读写争用，为每个端口提供争用覆盖信号。 集成电路可以包括具有用于每个端口的多个通行口的写入电路，包括用于每个端口的写通行证和争用通行证。 写入通道可以用来自相应端口的数据信号输入。 可以基于相对的争用覆盖信号，从相对端口输入具有数据信号的争用通行证。