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公开(公告)号：US20240013025A1
公开(公告)日：2024-01-11
申请号：US17982995
申请日：2022-11-08
发明人： Junwen LUO , Shengcheng WANG , Jiansong ZHANG
摘要： This application describes chiplet-based neuromorphic systems, devices, and chips. An exemplary chiplet-based neuromorphic system may include: a plurality of neuron processing entities (NPE); a plurality of chiplets each comprising a plurality of switches and a group of NPEs from the plurality of NPEs; and a plurality of interposers each comprising a plurality of routers and a group of chiplets from the plurality of chiplets; wherein each of the plurality of switches within each chiplet connects to one or more of the group of NPEs, and the plurality of switches within the each chiplet are organized in a tree topology; wherein each of the plurality of routers within each interposers connects to one or more of the group of chiplets, and the plurality of routers within the each interposer are organized in a tree topology.
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公开(公告)号：US20240005127A1
公开(公告)日：2024-01-04
申请号：US18070418
申请日：2022-11-28
发明人： Yijin GUAN , Dimin NIU , Shengcheng WANG , Shuangchen LI , Hongzhong ZHENG
CPC分类号： G06N3/04 , G06F1/1632
摘要： This application describes systems and methods for facilitating memory access for graph neural network (GNN) processing. An example system includes a plurality of processing units, each configured to perform graph neural network (GNN) processing; and a plurality of memory extension cards, each configured to store graph data for the GNN processing, wherein: each of the plurality of processing units is communicatively coupled with three other processing units via one or more interconnects respectively; the plurality of processing units are communicatively coupled with the plurality of memory extension cards respectively; and each of the plurality of memory extension cards includes a graphic access engine circuitry configured to acceleratre GNN memory access.
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公开(公告)号：US20220350526A1
公开(公告)日：2022-11-03
申请号：US17866403
申请日：2022-07-15
发明人： Dimin NIU , Yijin GUAN , Shengcheng WANG , Yuhao WANG , Shuangchen LI , Hongzhong ZHENG
IPC分类号： G06F3/06
摘要： The presented systems enable efficient and effective network communications. The presented systems enable efficient and effective network communications. In one embodiment a memory device includes a memory module, including a plurality of memory chips configured to store information; and an inter-chip network (ICN)/shared smart memory extension (SMX) memory interface controller (ICN/SMX memory interface controller) configured to interface between the memory module and an inter-chip network (ICN), wherein the ICN is configured to communicatively couple the memory device to a parallel processing unit (PPU). In one exemplary implementation, the ICN/SMX memory controller includes a plurality of package buffers, an ICN physical layer interface, a PRC/MAC interface, and a switch. The memory device and be a memory card including memory module (e.g., DDR DIMM, etc.).
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公开(公告)号：US20240061780A1
公开(公告)日：2024-02-22
申请号：US18450663
申请日：2023-08-16
发明人： Lide DUAN , Bowen HUANG , Qichen ZHANG , Shengcheng WANG , Yen-Kuang CHEN , Hongzhong ZHENG
IPC分类号： G06F12/0811 , G06F12/0846
CPC分类号： G06F12/0811 , G06F12/0848 , G06F2212/1021
摘要： A computer-implemented method for allocating memory bandwidth of multiple CPU cores in a server includes: receiving an access request to a last level cache (LLC) shared by the multiple CPU cores in the server, the access request being sent from a core with a private cache holding copies of frequently accessed data from a memory; determining whether the access request is an LLC hit or an LLC miss; and controlling a memory bandwidth controller based on the determination. The memory bandwidth controller performs a memory bandwidth throttling to control a request rate between the private cache and the last level cache. The LLC hit of the access request causes the memory bandwidth throttling initiated by the memory bandwidth controller to be disabled and the LLC miss of the access request causes the memory bandwidth throttling initiated by the memory bandwidth controller to be enabled.
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公开(公告)号：US20240004830A1
公开(公告)日：2024-01-04
申请号：US17982450
申请日：2022-11-07
发明人： Qichen ZHANG , Lide DUAN , Shengcheng WANG
CPC分类号： G06F15/8046 , G06F9/544 , G06F7/50 , G06F7/523
摘要： Embodiments of the present disclosure includes a processor. The processor may include a systolic array of processing elements; a first group of buffers coupled to the systolic array, wherein the first group comprises one or more first buffers; a second group of buffers coupled to the systolic array, wherein the second group comprises one or more second buffers; an accumulator coupled to the systolic array; and a third group of buffers coupled to the accumulator, wherein the third group comprises one or more third buffers.
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