公开(公告)号：US20250112812A1

公开(公告)日：2025-04-03

申请号：US18734903

申请日：2024-06-05

Applicant: Apple Inc.

Inventor： Adrian Ispas ,  Robert Dallinger ,  Christoph Angerer ,  Christian Mayer

IPC: H04L27/26

Abstract: An electronic device may include crest factor reduction circuitry having a clip and filter block and a frequency shift block. The crest factor reduction circuitry may receive an input signal and generate an output signal based on the input signal. The output signal may have a reduced peak-to-average power ratio relative to the input signal. The electronic device may also include a transmitter coupled to the crest factor reduction circuitry and configured to transmit a radio frequency signal based on the output signal.

公开(公告)号：US20240088924A1

公开(公告)日：2024-03-14

申请号：US17941905

申请日：2022-09-09

Applicant: Apple Inc.

Inventor： Stephan Henzler ,  Nicholas Preyss ,  Jochen Schrattenecker ,  Andreas Langer ,  Alexander Klinkan ,  Christoph Hepp ,  Christoph Angerer

IPC: H04B1/04 ,  H04L5/00 ,  H04W56/00

CPC classification number: H04B1/0458 ,  H04L5/0048 ,  H04W56/005 ,  H04B2001/0408

Abstract: Wireless circuitry can include a processor that generates a baseband signal, an upconversion circuit that upconverts the baseband signals to a radio-frequency signal, and an amplifier that amplifies the radio-frequency signal. A tunable delay circuit can be used to selectively delay generation of the radio-frequency signal or to delay generation of another signal intended for the radio-frequency amplifier. The tunable delay circuit can be controlled using a closed-loop delay adaptation scheme. A feedback receiver that is coupled to an output of the amplifier can be used to generate a demodulated signal. A delay error measurement circuit can be used to receive the demodulated signal, to detect a peak by monitoring when an envelope of the demodulated signal crosses a threshold level, to compute an amount of asymmetry in the detected peak, and to output a signal that is used to control the tunable delay circuit.