公开(公告)号：US20200350919A1

公开(公告)日：2020-11-05

申请号：US16401737

申请日：2019-05-02

Applicant: Apple Inc.

Inventor： Cristian Marcu ,  Feng Zhao ,  Wei Deng ,  Chunwei Chang ,  Robert K. Kong ,  Saeed Chehrazi

IPC: H03L7/18 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099

Abstract: In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.