公开(公告)号：US20230376448A1

公开(公告)日：2023-11-23

申请号：US17664632

申请日：2022-05-23

Applicant: Apple Inc.

Inventor： Xiaoning Nie ,  Mathias Kohlenz ,  Jin-Soo Yoo

IPC: G06F15/80

CPC classification number: G06F15/8061

Abstract: A merge sort circuit can include a parallel merge sort core that performs a partial merge on two input tuples, each containing a number P of data elements sorted according to a sort key, to produce a sorted output tuple of P data elements. Input data blocks to be merged can be stored in first and second block buffers. The block buffers can receive data from a vector memory read interface that reads groups of at least P data elements at a time. Loading of data elements into the block buffers can be based on respective fill levels of the block buffers.

公开(公告)号：US11803509B1

公开(公告)日：2023-10-31

申请号：US17664632

申请日：2022-05-23

Applicant: Apple Inc.

Inventor： Xiaoning Nie ,  Mathias Kohlenz ,  Jin-Soo Yoo

IPC: G06F15/80

CPC classification number: G06F15/8061

Abstract: A merge sort circuit can include a parallel merge sort core that performs a partial merge on two input tuples, each containing a number P of data elements sorted according to a sort key, to produce a sorted output tuple of P data elements. Input data blocks to be merged can be stored in first and second block buffers. The block buffers can receive data from a vector memory read interface that reads groups of at least P data elements at a time. Loading of data elements into the block buffers can be based on respective fill levels of the block buffers.