公开(公告)号：US20250093932A1

公开(公告)日：2025-03-20

申请号：US18468467

申请日：2023-09-15

Applicant: Apple Inc.

Inventor： John G. DORSEY ,  Bryan R. Hinch ,  Ronit Banerjee ,  Karthic A. Palaniappan

IPC: G06F1/28

Abstract: Some embodiments include a system, apparatus, method, and computer program product for memory hierarchy power management. Some embodiments include a performance controller that balances memory hierarchy power and compute power to maintain package-level power efficiency of a systems-on-a-chip (SoC)-memory package. The performance controller can determine a ratio of memory hierarchy power to compute agent power, compare the ratio against a threshold value, and based on the comparison, determine how to manage memory hierarchy power. When the energy costs of the memory hierarchy power are large relative to the energy costs of the compute agent power, some embodiments include changing a performance state of a fabric and/or memory to increase the power efficiency of the overall SoC-memory package, even though a number of memory stall cycles experienced by the compute agent may increase.