公开(公告)号：US20240329990A1

公开(公告)日：2024-10-03

申请号：US18740430

申请日：2024-06-11

Applicant: Apple Inc.

Inventor： Deepankar Duggal ,  Kulin N Kothari ,  Mridul Agarwal ,  Chang Xu ,  Yanran Yang ,  Richard F Russo ,  Yuan C Chou ,  Douglas C Holman

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/30087 ,  G06F9/3802 ,  G06F9/522

Abstract: A system, e.g., a system on a chip (SOC), may include one or more processors. A processor may execute an instruction synchronization barrier (ISB) instruction to enforce an ordering constraint on instructions. To execute the ISB instruction, the processor may determine whether contexts of the processor required for execution of instructions older than the ISB instruction are consumed for the older instructions. Responsive to determining that the contexts are consumed for the older instructions, the processor may initiate fetching of an instruction younger than the ISB instruction, without waiting for the older instructions to retire.

公开(公告)号：US12045615B1

公开(公告)日：2024-07-23

申请号：US17933040

申请日：2022-09-16

Applicant: Apple Inc.

Inventor： Deepankar Duggal ,  Kulin N Kothari ,  Mridul Agarwal ,  Chang Xu ,  Yanran Yang ,  Richard F Russo ,  Yuan C Chou ,  Douglas C Holman

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/30087 ,  G06F9/3802 ,  G06F9/522

Abstract: A system, e.g., a system on a chip (SOC), may include one or more processors. A processor may execute an instruction synchronization barrier (ISB) instruction to enforce an ordering constraint on instructions. To execute the ISB instruction, the processor may determine whether contexts of the processor required for execution of instructions older than the ISB instruction are consumed for the older instructions. Responsive to determining that the contexts are consumed for the older instructions, the processor may initiate fetching of an instruction younger than the ISB instruction, without waiting for the older instructions to retire.