公开(公告)号：US20240053962A1

公开(公告)日：2024-02-15

申请号：US17885364

申请日：2022-08-10

Applicant: Apple Inc.

Inventor： Michael L. Liu ,  Yash H. Malviya

IPC: G06F7/50 ,  G06F7/02

CPC classification number: G06F7/50 ,  G06F7/02

Abstract: An integrated circuit can include absolute difference circuitry configured to compute an absolute difference value. The absolute difference circuitry may include a comparison logic, a single adder, and a multiplexer. The comparison logic may receive a first input value and a second input value and may generate a comparison value based on whether the first input value exceeds the second input value. The adder may compute a sum of the first input value, an inverted version of the second input value, and the comparison value. The multiplexer may receive the sum and an inverted version of the sum and may output either the sum or the inverted version of the sum based on the comparison value to produce the absolute difference value.