公开(公告)号：US20230037714A1

公开(公告)日：2023-02-09

申请号：US17396452

申请日：2021-08-06

Applicant: Arm Limited

Inventor： Alejandro Rico Carro ,  Saurabh Pijuskumar Sinha ,  Douglas James Joseph ,  Tiago Rogerio Muck

IPC: H04L12/775 ,  H04L12/933 ,  H04L12/26 ,  G06F15/78

Abstract: Various implementations described herein refer to a device having a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first network that links nodes together in the first layer. The device may have a second network that links the nodes in the first layer together by way of the second layer so as to reduce latency related to data transfer between the nodes.