公开(公告)号：US12197916B2

公开(公告)日：2025-01-14

申请号：US18006813

申请日：2021-07-08

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Matthew Lucien Evans ,  Jelena Milanovic

IPC: G06F9/30 ,  G06F9/38

Abstract: Instruction decoder to decode processing instructions; one or more first registers; first processing circuitry to execute the decoded processing instructions in a first processing mode and configured to execute the decoded processing instructions using the one or more first registers; and control circuitry to execute the decoded processing instructions in a second processing mode using one or more second registers; the instruction decoder being configured to decode processing instructions selected from a first instruction set and a second instruction set in the second processing mode, in which one or both of the first and second instruction sets comprises at least one unique instruction set; the instruction decoder configured to decode one or more mode change instructions to change between the first and second processing mode; and the first processing circuitry configured to change the current processing mode between the first and second processing mode responding to executing mode change instruction.

公开(公告)号：US20240329996A1

公开(公告)日：2024-10-03

申请号：US18579804

申请日：2022-06-22

Applicant: Arm Limited

Inventor： Alejandro Martinez Vicente ,  Nigel John Stephens ,  Jelena Milanovic

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30036

Abstract: Apparatuses, methods and programs are disclosed relating to the predication of multiple vectors in vector processing. An encoding of predicate information is disclosed which comprises an element size and an element count, wherein the predicate information comprises a multiplicity of consecutive identical predication indicators given by the element count, each predication indicator corresponding to the element size.

公开(公告)号：US12288071B2

公开(公告)日：2025-04-29

申请号：US18006806

申请日：2021-07-05

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  Jelena Milanovic ,  David Hennah Mansell

IPC: G06F9/30

Abstract: A data transfer instruction is provided which specifies register addressing information for identifying a target portion of the register storage. In response to the data transfer instruction, instruction decoding circuitry controls processing circuitry to perform a data transfer operation to transfer data to or from the target portion of the register storage. The register addressing information includes at least: a base register identifier identifying a base register of the register storage for storing a base value; and an immediate value specified in an encoding of the data transfer instruction, the immediate value representing a value to be added to the base value to provide an index value for selecting the target portion of the register storage. This can be useful to provide an instruction set architecture which supports code that is scalable to variable data structure sizes, and which supports loop unrolling.

公开(公告)号：US11288066B2

公开(公告)日：2022-03-29

申请号：US16626701

申请日：2018-06-08

Applicant: ARM LIMITED

Inventor： David Hennah Mansell ,  Rune Holm ,  Ian Michael Caulfield ,  Jelena Milanovic

IPC: G06F9/302 ,  G06F9/30 ,  G06F17/16

Abstract: Techniques for performing matrix multiplication in a data processing apparatus are disclosed, comprising apparatuses, matrix multiply instructions, methods of operating the apparatuses, and virtual machine implementations. Registers, each register for storing at least four data elements, are referenced by a matrix multiply instruction and in response to the matrix multiply instruction a matrix multiply operation is carried out. First and second matrices of data elements are extracted from first and second source registers, and plural dot product operations, acting on respective rows of the first matrix and respective columns of the second matrix are performed to generate a square matrix of result data elements, which is applied to a destination register. A higher computation density for a given number of register operands is achieved with respect to vector-by-element techniques.

公开(公告)号：US11074214B2

公开(公告)日：2021-07-27

申请号：US16531210

申请日：2019-08-05

Applicant: Arm Limited

Inventor： Jelena Milanovic ,  Lee Evan Eisen ,  Nigel John Stephens

IPC: G06F9/30 ,  G06F15/80

Abstract: Data processing apparatus comprises processing circuitry to apply processing operations to one or more data items of a linear array comprising a plurality, n, of data items at respective positions in the linear array, the processing circuitry being configured to access an array of n×n storage locations, where n is an integer greater than one, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to an array access instruction, to control the instruction processing circuitry to access, as a linear array, a set of n storage locations arranged in an array direction selected, under control of the array access instruction, from a set of candidate array directions comprising at least a first array direction and a second array direction different to the first array direction.