公开(公告)号：US20250077499A1

公开(公告)日：2025-03-06

申请号：US18240632

申请日：2023-08-31

Applicant: Arm Limited ,  Barcelona Supercomputing Center - Centro Nacional de Supercomputación

Inventor： Marco SIRACUSA ,  Joshua RANDALL ,  Douglas James JOSEPH ,  Miquel MORETÓ PLANAS ,  Adrià ARMEJACH SANOSA

IPC: G06F16/22

Abstract: A data structure marshalling unit for a processor comprises data structure traversal circuitry to perform data structure traversal processing according to a dataflow architecture. The data structure traversal circuitry comprises two or more layers of traversal circuit units, each layer comprising two or more parallel lanes of traversal circuit units. Each traversal circuit unit triggers loading, according to a programmable iteration range, of at least one stream of elements of at least one data structure from data storage circuitry. For at least one programmable setting for the data structure traversal circuitry, the programmable iteration range for a given traversal circuit unit in a downstream layer is dependent on one or more elements of the at least one stream of elements loaded by at least one traversal circuit unit in an upstream layer. Output interface circuitry outputs to the data storage circuitry at least one vector of elements loaded by respective traversal circuit units in a given active layer of the data structure traversal circuitry.

公开(公告)号：US20210294743A1

公开(公告)日：2021-09-23

申请号：US16821271

申请日：2020-03-17

Applicant: Arm Limited

Inventor： Joshua RANDALL ,  Jesse Garrett BEU

IPC: G06F12/0815 ,  G06F12/0895 ,  G06F12/0884 ,  G06F12/02 ,  G06F12/14

Abstract: An apparatus is provided for receiving requests from a plurality of processing units, at least some of which may have associated cache storage. A snoop unit implements a cache coherency protocol when a request received by the apparatus identifies a cacheable memory address. Snoop filter storage is provided comprising an N-way set associative storage structure with a plurality of entries. Each entry stores coherence data for an associated address range identifying a memory block, and the coherence data is used to determine which cache storages need to be subjected to a snoop operation when implementing the cache coherency protocol in response to a received request. The snoop filter storage stores coherence data for memory blocks of at least a plurality P of different size granularities, and is organised as a plurality of at least P banks that are accessible in parallel, where each bank has entries within each of the N-ways of the snoop filter storage. The snoop control circuitry controls access to the snoop filter storage, and is responsive to a received address to create a group of indexes, the group of indexes comprising an index for each different size granularity amongst the P different size granularities, and each index in the group being constrained so as to identify an entry in a different bank of the snoop filter storage. The snoop control circuitry uses the group of indexes to perform a lookup operation in parallel within the snoop filter storage in order to determine, taking into account each of the different size granularities, whether an entry stores coherence data for the received address.

公开(公告)号：US20200142826A1

公开(公告)日：2020-05-07

申请号：US16182741

申请日：2018-11-07

Applicant: Arm Limited

Inventor： Joshua RANDALL ,  Alejandro Rico CARRO ,  Jose Alberto JOAO ,  Richard William EARNSHAW ,  Alasdair GRANT

IPC: G06F12/0802

Abstract: Aspects of the present disclosure relate to an apparatus comprising a requester master processing device having an associated private cache storage to store data for access by the requester master processing device. The requester master processing device is arranged to issue a request to modify data that is associated with a given memory address and stored in a private cache storage associated with a recipient master processing device. The private cache storage associated with the recipient master processing device is arranged to store data for access by the recipient master processing device. The apparatus further comprises the recipient master processing device having its private cache storage. One of the recipient master processing device and its associated private cache storage is arranged to perform the requested modification of the data while the data is stored in the cache storage associated with the recipient master processing device.

公开(公告)号：US20230139212A1

公开(公告)日：2023-05-04

申请号：US17905566

申请日：2021-01-18

Applicant: Arm Limited

Inventor： Joshua RANDALL ,  Jesse Garrett BEU

IPC: G06F12/02 ,  G06F12/0871 ,  G06F12/0831

Abstract: An apparatus and method are provided for receiving a request from a plurality of processing units, where multiple of those processing units have associated cache storage. A snoop unit is used to implement a cache coherency protocol when a request is received that identifies a cacheable memory address. The snoop unit has snoop filter storage comprising a plurality of snoop filter tables organized in a hierarchical arrangement. The snoop filter tables comprise a primary snoop filter table at a highest level in the hierarchy, and each snoop filter table at a lower level in the hierarchy forms a backup snoop filter table for an adjacent snoop filter table at a higher level in the hierarchy. Each snoop filter table is arranged as a multi-way set associative storage structure, and each backup snoop filter table has a different number of sets than are provided in the adjacent snoop filter table.