公开(公告)号：US20230037714A1

公开(公告)日：2023-02-09

申请号：US17396452

申请日：2021-08-06

Applicant: Arm Limited

Inventor： Alejandro Rico Carro ,  Saurabh Pijuskumar Sinha ,  Douglas James Joseph ,  Tiago Rogerio Muck

IPC: H04L12/775 ,  H04L12/933 ,  H04L12/26 ,  G06F15/78

Abstract: Various implementations described herein refer to a device having a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first network that links nodes together in the first layer. The device may have a second network that links the nodes in the first layer together by way of the second layer so as to reduce latency related to data transfer between the nodes.

公开(公告)号：US11263137B2

公开(公告)日：2022-03-01

申请号：US16884359

申请日：2020-05-27

Applicant: Arm Limited

Inventor： Jose Alberto Joao ,  Tiago Rogerio Muck ,  Joshua Randall ,  Alejandro Rico Carro ,  Bruce James Mathewson

IPC: G06F12/00 ,  G06F12/0842 ,  G06F12/0875

Abstract: A method and apparatus is disclosed for transferring data from a first processor core to a second processor core. The first processor core executes a stash instruction having a first operand associated with a data address of the data. A second processor core is determined to be a stash target for a stash message, based on the data address or a second operand. A stash message is sent to the second processor core, notifying the second processor core of the written data. Responsive to receiving the stash message, the second processor core can opt to store the data in its cache. The data may be included in the stash message or retrieved in response to a read request by the second processing core. The second processor core may be determined by prediction based, at least in part, on monitored data transactions.

公开(公告)号：US20210374059A1

公开(公告)日：2021-12-02

申请号：US16884359

申请日：2020-05-27

Applicant: Arm Limited

Inventor： Jose Alberto Joao ,  Tiago Rogerio Muck ,  Joshua Randall ,  Alejandro Rico Carro ,  Bruce James Mathewson

IPC: G06F12/0842 ,  G06F12/0875

Abstract: A method and apparatus is disclosed for transferring data from a first processor core to a second processor core. The first processor core executes a stash instruction having a first operand associated with a data address of the data. A second processor core is determined to be a stash target for a stash message, based on the data address or a second operand. A stash message is sent to the second processor core, notifying the second processor core of the written data. Responsive to receiving the stash message, the second processor core can opt to store the data in its cache. The data may be included in the stash message or retrieved in response to a read request by the second processing core. The second processor core may be determined by prediction based, at least in part, on monitored data transactions.