公开(公告)号：US06882512B2

公开(公告)日：2005-04-19

申请号：US09942271

申请日：2001-08-29

Applicant: Armand Castillejo ,  Christophe Pinatel ,  Frédéric Bossu ,  Christophe Garnier

Inventor： Armand Castillejo ,  Christophe Pinatel ,  Frédéric Bossu ,  Christophe Garnier

IPC: H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0255 ,  H01L27/0248

Abstract: An integrated circuit including an output pad, an output block coupled to the output pad via a capacitor, a first one-way conduction element for connecting the pad to a supply line when the voltage on the pad exceeds the voltage of the supply line by a first threshold voltage, a second one-way conduction element for connecting the pad to the circuit ground when the voltage on the pad is smaller than the ground voltage by a second threshold voltage, a resistor coupled on the one hand to the output pad and on the other hand to the supply line via a switch which is turned off when the circuit is idle and which is turned on when the circuit is in a normal operating mode.

Abstract translation: 一种集成电路，包括输出焊盘，经由电容器耦合到输出焊盘的输出块;第一单向导电元件，用于当焊盘上的电压超过电源线的电压时，将焊盘连接到电源线 第一阈值电压，第二单向导电元件，用于当焊盘上的电压小于接地电压第二阈值电压时，将焊盘连接到电路接地;一方面将电阻耦合到输出焊盘， 另一方面通过在电路空闲时断开的开关和在电路处于正常工作模式时导通的开关。

公开(公告)号：US07751793B2

公开(公告)日：2010-07-06

申请号：US11294802

申请日：2005-12-06

Applicant: Armand Castillejo ,  Fabienne Rerat

Inventor： Armand Castillejo ,  Fabienne Rerat

IPC: H04B1/26 ,  H01F5/00

CPC classification number: H01F21/12 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2021/125 ,  H01L23/5227 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit including a structure of inductances on a semiconductor substrate, intended for operating at frequencies greater than several hundreds of MHz, including a first inductance formed by a conductive track and having first and second terminals respectively connected to each of the two ends of the conductive track, including a second inductance formed by the conductive track between the second terminal and any intermediary point of the conductive track connected to a third terminal, said second and third terminals forming the two terminals of the second inductance, and means for setting the third terminal to high impedance when the first inductance is used.

Abstract translation: 一种集成电路，包括在半导体衬底上的电感结构，用于在大于几百MHz的频率下工作，包括由导电轨迹形成的第一电感，并具有分别连接到导电轨道的两端的第一和第二端子 导电轨道，包括由第二端子和连接到第三端子的导电轨道的任何中间点之间的导电轨迹形成的第二电感，所述第二和第三端子形成第二电感的两个端子，以及用于设置第三电感的装置 当使用第一电感时端子到高阻抗。

公开(公告)号：US20060084401A1

公开(公告)日：2006-04-20

申请号：US11294802

申请日：2005-12-06

Applicant: Armand Castillejo ,  Fabienne Rerat

Inventor： Armand Castillejo ,  Fabienne Rerat

IPC: H04B1/16

CPC classification number: H01F21/12 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2021/125 ,  H01L23/5227 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit including a structure of inductances on a semiconductor substrate, intended for operating at frequencies greater than several hundreds of MHz, including a first inductance formed by a conductive track and having first and second terminals respectively connected to each of the two ends of the conductive track, including a second inductance formed by the conductive track between the second terminal and any intermediary point of the conductive track connected to a third terminal, said second and third terminals forming the two terminals of the second inductance, and means for setting the third terminal to high impedance when the first inductance is used.

公开(公告)号：US06993313B2

公开(公告)日：2006-01-31

申请号：US09918792

申请日：2001-07-30

Applicant: Armand Castillejo ,  Fabienne Rerat

Inventor： Armand Castillejo ,  Fabienne Rerat

IPC: H04B1/28 ,  H04B1/18 ,  H05F5/00

CPC classification number: H01F21/12 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2021/125 ,  H01L23/5227 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit including a structure of inductances on a semiconductor substrate, intended for operating at frequencies greater than several hundreds of MHz, including a first inductance formed by a conductive track and having first and second terminals respectively connected to each of the two ends of the conductive track, including a second inductance formed by the conductive track between the second terminal and any intermediary point of the conductive track connected to a third terminal, said second and third terminals forming the two terminals of the second inductance, and means for setting the third terminal to high impedance when the first inductance is used.

公开(公告)号：US06982463B2

公开(公告)日：2006-01-03

申请号：US10450009

申请日：2001-11-26

Applicant: Armand Castillejo

Inventor： Armand Castillejo

IPC: H01L23/62

CPC classification number: H01L23/10 ,  H01L23/585 ,  H01L23/60 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

Abstract: The integrated circuit includes a substrate SB incorporating a plurality of electronic components C1, C2 and a seal ring SR around the electronic components. It includes cold spot means VM, PG, BDG disposed between the electronic components and the seal ring. It further includes electrostatic discharge protection means including an electrostatic discharge rail VM around the electronic components and constituting said cold spot means.

Abstract translation: 集成电路包括在电子部件周围包括多个电子部件C 1，C 2和密封环SR的基板SB。 它包括设置在电子部件和密封环之间的冷点装置VM，PG，BDG。 还包括静电放电保护装置，其包括电子部件周围的静电放电轨VM，构成所述冷点装置。