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    METHODS FOR MAKING SEMICONDUCTOR DEVICES USING NITRIDE CONSUMPTION LOCOS OXIDATION
    7.
    发明申请
    METHODS FOR MAKING SEMICONDUCTOR DEVICES USING NITRIDE CONSUMPTION LOCOS OXIDATION 审中-公开
    使用氮化物消耗LOCOS氧化制备半导体器件的方法

    公开(公告)号：US20100187602A1

    公开(公告)日：2010-07-29

    申请号：US12362321

    申请日：2009-01-29

    申请人： Debra S. Woolsey ,  Tony L. Olsen ,  Gordon K. Madson

    发明人： Debra S. Woolsey ,  Tony L. Olsen ,  Gordon K. Madson

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/76202 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66719 ,  H01L29/66734

    摘要： Semiconductor devices and methods for making such devices using nitride consumption LOCOS oxidation are described. The semiconductor devices contain a planar field oxide structure that has been grown using a nitride layer as an oxidation mask. Once the field oxide structure has been grown, the nitride mask is not etched away, but rather converted to an oxide layer by an oxidation process using radicals of hydrogen and oxygen. The semiconductor devices also contain a shielded gate trench MOSFET that can be created using an oxide layer with an overlying nitride layer as the channel (sidewall) gate dielectric. An inter-poly-dielectric (IPD) layer can be formed from a thermally grown oxide which uses the nitride layer as a oxidation mask. The thickness of the IPD layer can be adjusted to any thickness needed with minimal effect of the channel gate dielectric layer. An oxidation process using radicals of hydrogen and oxygen can be preformed to consume the nitride layer and form the gate oxide in the channel region. Since the gate channel nitride acts as a barrier to the oxidation, the IPD oxide layer can be grown to any needed thickness with minimal oxidation to the channel gate and the nitride layer can be removed without any etching processes. Other embodiments are described.

    摘要翻译： 描述了使用氮化物消耗LOCOS氧化来制造这种器件的半导体器件和方法。 半导体器件包含已经使用氮化物层作为氧化掩模生长的平面场氧化物结构。 一旦场氧化物结构已经生长，则氮化物掩模不被蚀刻掉，而是通过使用氢和氧的自由基的氧化工艺转化为氧化物层。 半导体器件还包含可以使用具有上覆氮化物层作为沟道（侧壁）栅极电介质的氧化物层来产生的屏蔽栅极沟槽MOSFET。 可以由使用氮化物层作为氧化掩模的热生长氧化物形成多晶硅电介质（IPD）层。 IPD层的厚度可以通过沟道栅介质层的最小影响来调节到所需的任何厚度。 可以进行使用氢和氧的自由基的氧化过程以消耗氮化物层并在沟道区域中形成栅极氧化物。 由于栅极沟道氮化物作为氧化的屏障，所以可以将IPD氧化物层生长至任何所需的厚度，同时对沟道栅极进行最小的氧化，并且氮化物层可以在没有任何蚀刻工艺的情况下被去除。 描述其他实施例。

    Method and structure for shielded gate trench FET
    8.
    发明授权
    Method and structure for shielded gate trench FET 有权
    屏蔽栅沟槽FET的方法和结构

    公开(公告)号：US08497549B2

    公开(公告)日：2013-07-30

    申请号：US11848124

    申请日：2007-08-30

    申请人： Gordon K. Madson

    发明人： Gordon K. Madson

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734

    摘要： A shielded gate field effect transistor includes a trench extending into a semiconductor region. A shield electrode is in a lower portion of the trench, and is insulated from the semiconductor region by a shield dielectric. The shield dielectric comprises first and second dielectric layers, the first dielectric layer extending between the second dielectric layer and the semiconductor region. The second dielectric layer comprises a material which during oxidation process inhibits growth of oxide along surfaces of the semiconductor region covered by the second dielectric layer. An inter-electrode dielectric overlies the shield electrode, and a gate dielectric lines upper trench sidewalls. A gate electrode is in an upper portion of the trench over the inter-electrode dielectric.

    摘要翻译： 屏蔽栅场效应晶体管包括延伸到半导体区域中的沟槽。 屏蔽电极位于沟槽的下部，并通过屏蔽电介质与半导体区域绝缘​​。 屏蔽电介质包括第一和第二介电层，第一介电层在第二介电层和半导体区之间延伸。 第二电介质层包括在氧化过程中抑制氧化物沿着由第二电介质层覆盖的半导体区域的表面生长的材料。 电极间电介质覆盖在屏蔽电极上，并且栅极介电线路上沟槽侧壁。 栅极电极位于电极间电介质上方的沟槽的上部。

    Method and Structure for Shielded Gate Trench FET
    9.
    发明申请
    Method and Structure for Shielded Gate Trench FET 有权
    屏蔽栅沟槽FET的方法和结构

    公开(公告)号：US20090050959A1

    公开(公告)日：2009-02-26

    申请号：US11848124

    申请日：2007-08-30

    申请人： Gordon K. Madson

    发明人： Gordon K. Madson

    IPC分类号： H01L29/94 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734

    摘要： A shielded gate field effect transistor includes a trench extending into a semiconductor region. A shield electrode is in a lower portion of the trench, and is insulated from the semiconductor region by a shield dielectric. The shield dielectric comprises first and second dielectric layers, the first dielectric layer extending between the second dielectric layer and the semiconductor region. The second dielectric layer comprises a material which during oxidation process inhibits growth of oxide along surfaces of the semiconductor region covered by the second dielectric layer. An inter-electrode dielectric overlies the shield electrode, and a gate dielectric lines upper trench sidewalls. A gate electrode is in an upper portion of the trench over the inter-electrode dielectric.

    摘要翻译： 屏蔽栅场效应晶体管包括延伸到半导体区域中的沟槽。 屏蔽电极位于沟槽的下部，并通过屏蔽电介质与半导体区域绝缘​​。 屏蔽电介质包括第一和第二介电层，第一介电层在第二介电层和半导体区之间延伸。 第二电介质层包括在氧化过程中抑制氧化物沿着由第二电介质层覆盖的半导体区域的表面生长的材料。 电极间电介质覆盖在屏蔽电极上，并且栅极介电线路上沟槽侧壁。 栅极电极位于电极间电介质上方的沟槽的上部。

    Method of manufacturing a trench MOSFET using selective growth epitaxy
    10.
    发明授权
    Method of manufacturing a trench MOSFET using selective growth epitaxy 失效
    使用选择性生长外延制造沟槽MOSFET的方法

    公开(公告)号：US06635534B2

    公开(公告)日：2003-10-21

    申请号：US09780040

    申请日：2001-02-09

    申请人： Gordon K. Madson

    发明人： Gordon K. Madson

    IPC分类号： H01L21336

    CPC分类号： H01L29/7813 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823487 ,  H01L29/42368

    摘要： A method of manufacturing a trench structure for a trench MOSFET, including the steps of providing a semiconductor substrate having a major surface, forming a dielectric pillar on the substrate major surface (the dielectric pillar extending substantially perpendicularly from the major surface of the substrate), selectively forming a semiconductor layer around the dielectric pillar, and removing a predetermined length of the dielectric pillar to create a trench in the substrate, the trench defined by sidewalls and a bottom. The method permits the controlled formation of a dielectric plug at the bottom of the trench, the plug having predetermined dimensions.

    摘要翻译： 一种制造用于沟槽MOSFET的沟槽结构的方法，包括以下步骤：提供具有主表面的半导体衬底，在衬底主表面（介质柱从衬底的主表面大致垂直延伸）形成介电柱， 选择性地在电介质柱周围形成半导体层，以及去除预定长度的电介质柱以在衬底中形成沟槽，沟槽由侧壁和底部限定。 该方法允许在沟槽的底部受控地形成电介质塞，塞具有预定的尺寸。