公开(公告)号：US10833691B1

公开(公告)日：2020-11-10

申请号：US16696463

申请日：2019-11-26

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Cameron Huang ,  Randall M. White

IPC: H03M1/10

Abstract: An analog to digital converter is disclosed that is designed to receive a differential analog signal and includes a signal chopping circuit and a successive approximation register (SAR) coupled to the signal chopping circuit. The signal chopping circuit is designed to invert a polarity of the differential analog signal and includes a first switching circuit having a first transistor and a second switching circuit having a second transistor. A gate of the first transistor and a gate of the second transistor is each coupled to a same bootstrap capacitor. Coupling both switching circuits to the same bootstrap capacitor (as opposed to separate bootstrap capacitors) greatly frees up space on the die or chip.

公开(公告)号：US10778155B2

公开(公告)日：2020-09-15

申请号：US16211049

申请日：2018-12-05

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Randall M. White

IPC: H03F3/45 ,  H03F1/32 ,  H03F1/02

Abstract: A dynamic differential amplifier includes: gain transistors to drive with differential input voltage levels; sample capacitors having first terminals to ramp from an initial voltage level to differential amplified voltage levels of the input voltage levels in response to the driven gain transistors; and adjustment circuits to adjust the amplified voltage levels in the direction of the initial voltage level by an offset voltage level. In some cases, second terminals of the sample capacitors are a common-mode node to maintain a common-mode voltage level midway between the ramping voltage levels of the first terminals. In some cases, the dynamic differential amplifier further includes a comparison circuit to compare the maintained common-mode voltage level to a threshold voltage level, wherein the first terminals of the sample capacitors stop ramping and the adjustment circuits adjust the amplified voltage levels in response to the compared common-mode voltage level reaching the threshold voltage level.

公开(公告)号：US20200259499A1

公开(公告)日：2020-08-13

申请号：US16273318

申请日：2019-02-12

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Randall M. White

IPC: H03M1/06 ,  H03M1/68 ,  H03M1/78

Abstract: Circuit techniques are disclosed for improving the SFDR of a DAC. In an embodiment, a DAC includes a resistor ladder network operably coupled to input logic circuitry and an output. The input logic circuitry receives a multi-bit input signal and effectively creates a plurality of processed input signals therefrom. The resistor ladder network is configured to receive the plurality of processed input signals and includes a corresponding plurality of current paths. Each current path includes: a current switch operably controlled by one of the processed input signals; a first resistor in series with the current switch; a second resistor in series with the first resistor; and a feedforward capacitor in parallel with the second resistor. The output is operably coupled to each of the plurality of current paths and is configured to output an analog output signal that corresponds to the multi-bit input signal.

公开(公告)号：US20200186102A1

公开(公告)日：2020-06-11

申请号：US16211049

申请日：2018-12-05

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Randall M. White

IPC: H03F1/32 ,  H03F1/02 ,  H03F3/45

Abstract: A dynamic differential amplifier includes: gain transistors to drive with differential input voltage levels; sample capacitors having first terminals to ramp from an initial voltage level to differential amplified voltage levels of the input voltage levels in response to the driven gain transistors; and adjustment circuits to adjust the amplified voltage levels in the direction of the initial voltage level by an offset voltage level. In some cases, second terminals of the sample capacitors are a common-mode node to maintain a common-mode voltage level midway between the ramping voltage levels of the first terminals. In some cases, the dynamic differential amplifier further includes a comparison circuit to compare the maintained common-mode voltage level to a threshold voltage level, wherein the first terminals of the sample capacitors stop ramping and the adjustment circuits adjust the amplified voltage levels in response to the compared common-mode voltage level reaching the threshold voltage level.