-
1.发明授权Determining controlling pins for a tile module of a programmable logic device 有权确定可编程逻辑器件的瓦片模块的控制引脚公开(公告)号：US07451425B1
公开(公告)日：2008-11-11
申请号：US11502922
申请日：2006-08-11
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054
摘要： A processor-implemented method is provided for determining controlling pins of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of a tile module are input. Characterization data is input for a sub-module of the tile module that specifies a select input pin controlling a programmable function of the sub-module, which is either a multiplexer or a logic site. Characterization data is input for a configuration memory cell of the tile module that specifies a data output pin of the configuration memory cell. The controlling pin is determined for each select input pin of each instance of the sub-module of the tile module. The controlling pin of a select input pin is the data output pin of an instance of a configuration memory cell of the tile module. A specification is output of the select input pin and corresponding controlling pin.
摘要翻译： 提供了一种用于确定可编程逻辑器件（PLD）设计的控制引脚的处理器实现的方法。 输入描述PLD设计的网表和瓦片模块的标识。 为瓦片模块的子模块输入表征数据，该模块指定控制作为多路复用器或逻辑站点的子模块的可编程功能的选择输入引脚。 输入表示配置存储单元的数据输出引脚的瓦片模块的配置存储单元的特征数据。 为瓦片模块的子模块的每个实例的每个选择输入引脚确定控制引脚。 选择输入引脚的控制引脚是瓦片模块的配置存储单元的实例的数据输出引脚。 选择输入引脚和相应的控制引脚输出规格。
-
2.发明授权Determining programmable connections through a switchbox of a programmable logic device 有权通过可编程逻辑器件的开关盒确定可编程连接公开(公告)号：US07451424B1
公开(公告)日：2008-11-11
申请号：US11502911
申请日：2006-08-11
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054
摘要： A processor-implemented method is provided for determining programmable connections through a switchbox module of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of the switchbox module are input. Characterization data is input for each multiplexer module of the switchbox module. The characterization data specifies input pins and at least one output pin of the multiplexer module. The multiplexer module programmably connects each output pin to one of the input pins. Pins of the switchbox module are determined through which the programmable connections are provided via an instance of a multiplexer module of the switchbox module. Each pair of the pins of the switchbox module is determined that are functionally connected via at least one instance of the at least one multiplexer module, with each pair specifying a programmable connection. A specification of the programmable connections is output.
摘要翻译： 提供了一种处理器实现的方法，用于通过可编程逻辑器件（PLD）设计的开关盒模块来确定可编程连接。 输入描述PLD设计和识别开关盒模块的网表。 为开关盒模块的每个复用器模块输入特征数据。 表征数据指定多路复用器模块的输入引脚和至少一个输出引脚。 多路复用器模块可编程地将每个输出引脚连接到其中一个输入引脚。 确定开关盒模块的引脚，通过该引脚通过开关盒模块的多路复用器模块的实例提供可编程连接。 确定开关盒模块的每对引脚经由至少一个多路复用器模块的至少一个实例功能连接，每对指定可编程连接。 输出可编程连接的规格。
-
3.发明授权Determining indices of configuration memory cell modules of a programmable logic device 有权确定可编程逻辑器件的配置存储单元模块的索引公开(公告)号：US07451423B1
公开(公告)日：2008-11-11
申请号：US11502909
申请日：2006-08-11
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054 , H03K19/1737
摘要： A processor-implemented method is provided for determining first and second indices of cell instances of a configuration memory cell of a tile module of a programmable logic device (PLD) design. A netlist is input that describes the PLD design and includes the cell instances of the configuration memory cell. An identification of the tile module is input. Characterization data is input for each configuration memory cell specifying address and data input pins. Characterization data is input for each configuration control module specifying a first ordered set of address output pins and a second ordered set of data output pins. For each of the cell instances, the first index of an address output pin in the first ordered set and the second index of a data output pin in the second ordered set are determined and a specification is output of the cell instance and the first and second indices.
摘要翻译： 提供了一种处理器实现的方法，用于确定可编程逻辑器件（PLD）设计的瓦片模块的配置存储器单元的第一和第二索引的小区实例。 网表是描述PLD设计的输入，包括配置存储单元的单元实例。 输入瓦片模块的标识。 为每个配置存储单元指定地址和数据输入引脚输入特征数据。 为每个配置控制模块输入表征数据，指定地址输出引脚的第一有序集合和第二有序数据输出引脚集合。 对于每个小区实例，确定第一有序集合中的地址输出引脚的第一索引和第二有序集合中的数据输出引脚的第二索引，并且输出小区实例的规范，并且第一和第二 指数。
-
公开(公告)号：US07584448B1
公开(公告)日：2009-09-01
申请号：US11502936
申请日：2006-08-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A processor-implemented method is provided for constructing a model of a programmable logic device (PLD) design. A netlist is input that describes the PLD design. An identification is input of programmable tile modules that include a programmable resource, which is either programmable interconnect or programmable logic. A first characterization data is input for sub-modules of the programmable tile modules for the programmable resource. For each programmable tile module, the routing arcs of each programmable interconnect are generated. A second characterization data is input for a configuration memory cell module of the PLD design. A third characterization data is input for a configuration control module of the PLD design. A first map is generated that links each routing arc to a bit of configuration data for programming the programmable interconnect. A second map is generated that links each logic function to a bit of configuration data for programming the programmable logic.
摘要翻译： 提供了一种用于构建可编程逻辑器件（PLD）设计的模型的处理器实现的方法。 一个网表是描述PLD设计的输入。 识别是可编程块模块的输入，其包括可编程资源，可编程互连或可编程逻辑。 为可编程资源的可编程瓦片模块的子模块输入第一特征数据。 对于每个可编程瓦片模块，可以生成每个可编程互连的路由弧。 为PLD设计的配置存储单元模块输入第二表征数据。 为PLD设计的配置控制模块输入第三个特征数据。 生成第一个映射，其将每个路由选择电弧链接到用于编程可编程互连的配置数据位。 生成第二个映射，将每个逻辑功能链接到用于编程可编程逻辑的配置数据位。
-
5.发明授权公开(公告)号：US07472370B1
公开(公告)日：2008-12-30
申请号：US11502946
申请日：2006-08-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A processor-implemented method is provided for comparing connections in a graphical representation of a programmable logic device (PLD) design to connections in a netlist that describes the PLD design. The netlist and an identification of each tile are input. For each of the tiles, a specification is input of a graphical tile representation and connection representations that terminate at a boundary of the tile representation. A specification is input of an arrayed placement of occurrences of the tile representations. For each abutting pair of occurrences of the tile representations in the arrayed placement, the connection representations are determined that terminate at a shared portion of the boundaries of the tile representations of the abutting pair. For each of a plurality of positions within the shared portion of the boundaries of the tile representations of each abutting pair, a match is checked between the connection representations terminating at the position.
摘要翻译： 提供了一种处理器实现的方法，用于将可编程逻辑器件（PLD）设计的图形表示中的连接与描述PLD设计的网表中的连接进行比较。 输入网表和每个瓦片的标识。 对于每个瓦片，规范是在瓦片表示的边界处终止的图形瓦片表示和连接表示的输入。 一个规范是瓦片表示出现的阵列放置的输入。 对于阵列放置中的每个邻接的瓦片表示的邻接对，确定连接表示，其终止于邻接对的瓦片表示的边界的共享部分。 对于每个邻接对的瓦片表示的边界的共享部分内的多个位置中的每一个，在终止于该位置的连接表示之间检查匹配。
-
公开(公告)号：US07536668B1
公开(公告)日：2009-05-19
申请号：US11502923
申请日：2006-08-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A processor-implemented method is provided for determining networks of a tile module of a programmable logic device (PLD) design. A netlist describing the PLD design and a tile module identification are input. Characterization data is input for a sub-module of the tile module that specifies modeled pins of the sub-module, which is either a switchbox or a logic site. Connectivity pins of the tile module are determined. Each connectivity pin of one of the tile instances is connected in the netlist to a modeled pin of an instance of the sub-module within a tile instance. Networks of the tile module are determined that connect a first subset of the connectivity pins of the tile module and a second subset of the modeled pins of an instance of the sub-module within the tile module. A specification is output for each of the networks including the first subset and the second subset.
摘要翻译： 提供了一种用于确定可编程逻辑器件（PLD）设计的瓦片模块的网络的处理器实现的方法。 输入描述PLD设计和瓦片模块识别的网表。 为块模块的子模块输入特征数据，该子模块指定子模块的模型化引脚，子模块是开关盒或逻辑站点。 确定瓦片模块的连接引脚。 其中一个瓦片实例的每个连接引脚都连接到网表中，以实现瓦片实例中子模块实例的建模引脚。 确定瓦片模块的网络，其连接瓦片模块的连接引脚的第一子集和瓦片模块内的子模块的实例的建模引脚的第二子集。 为包括第一子集和第二子集的每个网络输出规范。
-
公开(公告)号：US07451420B1
公开(公告)日：2008-11-11
申请号：US11502937
申请日：2006-08-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5068
摘要： A processor-implemented method is provided for determining reachable pins functionally connected to a network of a netlist that describes a programmable logic device (PLD) design. A netlist and an identification of the network in the netlist are input. Characterization data is input for one or more repeater modules that specify a first set of functionally connected pins of the repeater module. A second set is initialized with the pins of the network. For each pin in the second set that is one of the functionally connected pins of a first set, an additional pin may be added to the second set for each of the pins of a network for each of the functionally connected pins. The adding is repeated for each additional pin added to the second set. A specification of the pins from the second set is output as the reachable pins.
摘要翻译： 提供了一种处理器实现的方法，用于确定功能上连接到描述可编程逻辑器件（PLD）设计的网表的网络的可达引脚。 输入网表和网表中的网络标识。 为指定中继器模块的第一组功能连接的引脚的一个或多个中继器模块输入特征数据。 第二组用网络的引脚初始化。 对于作为第一组的功能连接的引脚之一的第二组中的每个引脚，可以为每个功能连接的引脚的网络的每个引脚向第二组添加附加引脚。 对于添加到第二组的每个附加引脚重复添加。 输出第二组引脚的规格为可达引脚。
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.03 秒)
