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公开(公告)号:US20110003455A1
公开(公告)日:2011-01-06
申请号:US12801115
申请日:2010-05-24
申请人: Woong-Hee SOHN , Gil-Heyun CHOI , Byung-Hee KIM , Byung-Hak LEE , Tae-Ho CHA , Hee-Sook PARK , Jae-Hwa PARK , Geum-Jung SEONG
发明人: Woong-Hee SOHN , Gil-Heyun CHOI , Byung-Hee KIM , Byung-Hak LEE , Tae-Ho CHA , Hee-Sook PARK , Jae-Hwa PARK , Geum-Jung SEONG
IPC分类号: H01L21/336 , H01L21/76
CPC分类号: H01L21/823481 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L29/518 , H01L29/66545 , H01L29/78 , Y10S438/981
摘要: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPDX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPDX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
摘要翻译: 公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。 这些方法提供了常规GPDX工艺的替代方案,并提供改进的耐漏电性,而不会导致与GPDX工艺相关的增加的栅电极电阻的程度。 每种方法包括形成第一开口以暴露有源区域区域,在暴露部分上形成氧化控制区域,然后形成第二开口,由此暴露氧化控制区域的外围区域以形成栅极介电层 。 得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。
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公开(公告)号:US20080102615A1
公开(公告)日:2008-05-01
申请号:US11685644
申请日:2007-03-13
申请人: Byung-Hak LEE , Woong-Hee SOHN , Jae-Hwa PARK , Gil-Heyun CHOI , Byung-Hee KIM , Hee-Sook PARK
发明人: Byung-Hak LEE , Woong-Hee SOHN , Jae-Hwa PARK , Gil-Heyun CHOI , Byung-Hee KIM , Hee-Sook PARK
IPC分类号: H01L21/4763
CPC分类号: H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11568
摘要: One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.
摘要翻译: 用于形成半导体器件的方法的一个实施例可以包括在半导体衬底上形成栅极图案,并且在包括氢,氧和氮在内的气体环境中对栅极图案进行选择性再氧化处理。 当栅极图案包括隧道绝缘层,金属氮化物层和金属层时,选择性再氧化工艺会修复栅极图案的蚀刻损伤,同时防止金属氮化物层和钨电极的氧化。
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3.
公开(公告)号:US20120153500A1
公开(公告)日:2012-06-21
申请号:US13314575
申请日:2011-12-08
申请人: Kyoung-Hee KIM , Gil-Heyun CHOI , Kyu-Hee HAN , Byung-Lyul PARK , Byung-Hee KIM , Sang-Hoon AHN , Kwang-Jin MOON
发明人: Kyoung-Hee KIM , Gil-Heyun CHOI , Kyu-Hee HAN , Byung-Lyul PARK , Byung-Hee KIM , Sang-Hoon AHN , Kwang-Jin MOON
IPC分类号: H01L23/48 , H01L21/768
CPC分类号: H01L21/76898 , H01L21/7682 , H01L21/76831 , H01L23/3171 , H01L23/481 , H01L24/05 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/06181 , H01L2224/13022 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/451 , H01L2224/48245 , H01L2224/48247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06565 , H01L2924/00013 , H01L2924/01327 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2924/00014
摘要: A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.
摘要翻译: 半导体器件包括具有第一触点的顶表面,具有第二触点的底表面,穿透基板的通孔,在通孔的侧壁上的绝缘层结构,其中具有气隙的绝缘层结构, 所述贯通电极在所述绝缘层结构上具有上表面和下表面,所述贯通电极填充所述通孔,所述下表面是所述第二接触,以及金属布线,电连接到所述通孔的上表面,并电连接到 第一次接触。
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公开(公告)号:US20080073692A1
公开(公告)日:2008-03-27
申请号:US11773362
申请日:2007-07-03
申请人: Jang-Hee LEE , Geum-Jung SEONG , Byung-Hee KIM , Tae-Ho CHA , Hee-Sook PARK
发明人: Jang-Hee LEE , Geum-Jung SEONG , Byung-Hee KIM , Tae-Ho CHA , Hee-Sook PARK
IPC分类号: H01L29/788 , H01L21/336
CPC分类号: H01L29/7881 , H01L21/28061 , H01L29/66825
摘要: A method of forming a semiconductor device includes sequentially first and second tungsten silicide layers on a silicon layer. The first tungsten silicide layer is in a substantially amorphous state and a ratio of tungsten to silicon in the first tungsten silicide layer is about 1:4.5˜about 1:9.
摘要翻译: 形成半导体器件的方法在硅层上依次包括第一和第二硅化钨层。 第一硅化钨层处于基本非晶态,并且第一硅化钨层中钨与硅的比例为约1:4.5〜约1:9。
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公开(公告)号:US20160307842A1
公开(公告)日:2016-10-20
申请号:US15006265
申请日:2016-01-26
申请人: Jong-Min BAEK , Sang-Hoon AHN , Woo-Kyung YOU , Byung-Hee KIM , Young-Ju PARK , Nae-in LEE , Kyung-Min CHUNG
发明人: Jong-Min BAEK , Sang-Hoon AHN , Woo-Kyung YOU , Byung-Hee KIM , Young-Ju PARK , Nae-in LEE , Kyung-Min CHUNG
IPC分类号: H01L23/522 , H01L27/088 , H01L23/535 , H01L23/532
CPC分类号: H01L27/0886 , H01L21/823431 , H01L21/823475
摘要: A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.
摘要翻译: 半导体器件包括彼此间隔开的多个布线结构和绝缘夹层结构。 每个布线结构包括金属图案和覆盖金属图案的顶表面的侧壁,底表面和边缘部分并且不覆盖金属图案的顶表面的中心部分的阻挡图案。 绝缘层间结构包含其中的布线结构,并且在布线结构之间具有气隙。
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