摘要:
A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.
摘要:
A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.
摘要:
A liner-less tungsten contact is formed on a nickel-tungsten silicide with a tungsten rich surface. A tungsten-containing layer is formed using tungsten-containing fluorine-free precursors. The tungsten-containing layer may act as a glue layer for a subsequent nucleation layer or as the nucleation layer. The tungsten plug is formed by standard processes. The result is a liner-less tungsten contact with low resistivity.
摘要:
A method includes providing a substrate including a non-insulative, silicon-including region for silicidation, the substrate including one or more contaminants at a top surface thereof. A getter layer is deposited over the non-insulative, silicon-including region, the getter layer reacting with at least one of the one or more contaminants in the non-insulative, silicon-including region at approximately room temperature. The getter layer is removed, and siliciding of the non-insulative, silicon-including region is performed.
摘要:
A liner-less tungsten contact is formed on a nickel-tungsten silicide with a tungsten rich surface. A tungsten-containing layer is formed using tungsten-containing fluorine-free precursors. The tungsten-containing layer may act as a glue layer for a subsequent nucleation layer or as the nucleation layer. The tungsten plug is formed by standard processes. The result is a liner-less tungsten contact with low resistivity.
摘要:
A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.
摘要:
An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.
摘要:
A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.
摘要:
In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.
摘要:
A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc.