公开(公告)号：US11119524B1

公开(公告)日：2021-09-14

申请号：US16815505

申请日：2020-03-11

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Christopher M. Dougherty ,  Anindya Bhattacharya ,  Vaibhav Pandey ,  Ying Ou

IPC: G05F3/26

Abstract: A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror. The selectable output current mirror may also include switch control circuitry configured to selectively enable and disable the output leg from generating the output current by selectively enabling and disabling the drain path switch and the degeneration path switch and glitch mitigation circuitry coupled to the second non-gate terminal of the output leg transistor and configured to maintain the second non-gate terminal of the output leg transistor at a substantially-constant voltage during transitions between disabling of the degeneration path switch and enabling of the degeneration path switch.

公开(公告)号：US11799426B2

公开(公告)日：2023-10-24

申请号：US17537619

申请日：2021-11-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Johnny Klarenbeek ,  David P. Singleton ,  Morgan T. Prior ,  Jonathan T. Wigner ,  Christopher M. Dougherty ,  Qi Cai ,  Anindya Bhattacharya

IPC: H03F1/02 ,  H03F3/217 ,  H03F3/38

CPC classification number: H03F1/0233 ,  H03F3/217 ,  H03F2200/03 ,  H03F2200/105

Abstract: Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.