公开(公告)号：US06255899B1

公开(公告)日：2001-07-03

申请号：US09388164

申请日：1999-09-01

申请人： Claude L. Bertin ,  Anthony R. Bonaccio ,  Erik L. Hedberg ,  Howard L. Kalter ,  Thomas M. Maffitt ,  Jack A. Mandelman ,  Edward J. Nowak ,  William R. Tonti

发明人： Claude L. Bertin ,  Anthony R. Bonaccio ,  Erik L. Hedberg ,  Howard L. Kalter ,  Thomas M. Maffitt ,  Jack A. Mandelman ,  Edward J. Nowak ,  William R. Tonti

IPC分类号： H01L2500

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

摘要： An assembly is provided that includes an interposer having first and second substantially flat, opposed surfaces, and at least one speed critical signal line extending directly through the interposer from the first surface to the second surface. A first IC is coupled to the first surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. A second IC is coupled to the second surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. Preferably at least one non-speed critical signal line is provided within the interposer and is coupled to a second external connection mechanism of the first IC and/or the second IC for delivering non-speed critical signals thereto or for receiving such signals therefrom. A chip carrier having a cavity formed therein also may be provided wherein the second surface of the interposer is coupled to the chip carrier and the second IC is disposed within the cavity. One or more carrier signal lines may be provided within the chip carrier and coupled between the interposer and the second IC. The first and/or the second IC also may comprise control logic adapted to select a number of drivers within either IC that drive a particular signal line.

摘要翻译： 提供了一种组件，其包括具有第一和第二基本上平坦的相对表面的插入件以及至少一个直线从第一表面延伸到第二表面的速度临界信号线。 第一IC耦合到插入器的第一表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。 第二IC耦合到插入器的第二表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。 优选地，在插入器内提供至少一个非速度临界信号线，并且耦合到第一IC和/或第二IC的第二外部连接机构，用于向其递送非速度关键信号或用于从其接收这样的信号。 还可以提供其中形成有空腔的芯片载体，其中插入器的第二表面耦合到芯片载体，并且第二IC设置在空腔内。 可以在芯片载体内提供一个或多个载波信号线，并且耦合在插入器和第二IC之间。 第一和/或第二IC还可以包括适于选择驱动特定信号线的IC内的多个驱动器的控制逻辑。

公开(公告)号：US06369671B1

公开(公告)日：2002-04-09

申请号：US09281412

申请日：1999-03-30

申请人： Claude L. Bertin ,  Anthony R. Bonaccio ,  Howard L. Kalter ,  Thomas M. Maffitt ,  Jack A. Mandelman ,  Edward J. Nowak ,  William R. Tonti

发明人： Claude L. Bertin ,  Anthony R. Bonaccio ,  Howard L. Kalter ,  Thomas M. Maffitt ,  Jack A. Mandelman ,  Edward J. Nowak ,  William R. Tonti

IPC分类号： H01P1185

CPC分类号： G11C7/12

摘要： A semiconductor structure having a substrate, an insulator above a portion of the substrate, a conductor above the insulator; and at least two contact regions in the substrate on opposite sides of the portion of the substrate, wherein a voltage between the contact regions modulates a capacitance of the conductor.

摘要翻译： 一种具有衬底的半导体结构，在衬底的一部分上方的绝缘体，绝缘体上方的导体; 以及在所述衬底的所述部分的相对侧上的所述衬底中的至少两个接触区域，其中所述接触区域之间的电压调制所述导体的电容。

公开(公告)号：US06177818B1

公开(公告)日：2001-01-23

申请号：US09303508

申请日：1999-04-30

申请人： Claude L. Bertin ,  Anthony R. Bonaccio ,  Howard L. Kalter ,  Thomas M. Maffitt ,  Jack A. Mandelman ,  William R. Tonti

发明人： Claude L. Bertin ,  Anthony R. Bonaccio ,  Howard L. Kalter ,  Thomas M. Maffitt ,  Jack A. Mandelman ,  William R. Tonti

IPC分类号： H03B2100

CPC分类号： H03K19/09482 ,  H03K19/00361 ,  H03K19/018521

摘要： An off-chip driver circuit including an enhancement PFET, a depletion PFET, a depletion NFET and an enhancement NFET connected in series. The large enhancement PFET and large enhancement NFET turn off the OCD in tri-state and to turn off the unused half of the OCD to prevent overlap current when driving a ‘0’ or a ‘1’. A first gate signal is applied to the gate of the enhancement PFET and a second gate signal is applied to the enhancement NFET. A fixed voltage is connected to the gate of the depletion NFET and ground to gate of the depletion PFET. An output signal is obtained from a node between the depletion PFET and depletion NFET devices. In another embodiment, a reflection/overshoot sensor 60 is added. The output of sensor is connected to the body of a depletion PFET and an NFET. The feedback from sensor is such that the threshold voltage of the depletion devices are made more positive if the sensor detects that the output is being over-driven. A more positive threshold voltage will reduce the driver's IDS, but leaves the device in the linear mode.

摘要翻译： 包括增强型PFET，耗尽型PFET，耗尽型NFET和增强型NFET的片外驱动电路。 大增强型PFET和大增强型NFET在三态关闭OCD并关闭OCD的未使用的一半以防止在驱动“0”或“1”时重叠电流。 第一栅极信号被施加到增强PFET的栅极，并且第二栅极信号被施加到增强NFET。 固定电压连接到耗尽型NFET的栅极，并连接到耗尽PFET的栅极。 从耗尽PFET和耗尽NFET器件之间的节点获得输出信号。 在另一个实施例中，添加了反射/过冲传感器60。 传感器的输出连接到耗尽PFET和NFET的主体。 来自传感器的反馈使得如果传感器检测到输出被过驱动，则耗尽装置的阈值电压变得更为正。 更正的阈值电压将减少驾驶员的IDS，但使设备处于线性模式。

公开(公告)号：US06437385B1

公开(公告)日：2002-08-20

申请号：US09607094

申请日：2000-06-29

申请人： Claude L. Bertin ,  Thomas M. Maffitt ,  Wilbur D. Pricer ,  William R. Tonti

发明人： Claude L. Bertin ,  Thomas M. Maffitt ,  Wilbur D. Pricer ,  William R. Tonti

IPC分类号： H01L27108

CPC分类号： H01L27/10861 ,  H01L27/10832 ,  H01L28/55 ,  H01L28/87 ,  H01L29/66181 ,  H01L29/945

摘要： Use of different materials for different conductive films forming plates or electrodes of one or more capacitors formed in a trench in a body of semiconductor materials allow connections to be made selectively to the plates. The films may be undercut by different etchants at respective connection apertures to avoid formation of connections or connections made by doped polysilicon of different conductivities forming connections to some plates of similarly doped polysilicon and blocking diode junctions with oppositely doped polysilicon. The blocking diodes may include a compensation implant to adjust reverse breakdown characteristics and provide transient and electrostatic discharge protection.

摘要翻译： 对于形成在半导体材料体中的沟槽中的一个或多个电容器形成板或不同导电膜的不同材料的使用允许选择性地连接板。 这些膜可能在相应的连接孔处被不同的蚀刻剂削弱，以避免由不同导电性的掺杂多晶硅形成的连接或连接形成连接到具有相反掺杂多晶硅的类似掺杂多晶硅和阻塞二极管结的某些平板。 阻塞二极管可以包括补偿注入以调整反向击穿特性并提供瞬态和静电放电保护。

公开(公告)号：US06496037B1

公开(公告)日：2002-12-17

申请号：US09588202

申请日：2000-06-06

申请人： Claude L. Bertin ,  John A. Fifield ,  Thomas M. Maffitt ,  Wilbur D. Pricer ,  William R. Tonti

发明人： Claude L. Bertin ,  John A. Fifield ,  Thomas M. Maffitt ,  Wilbur D. Pricer ,  William R. Tonti

IPC分类号： H03K190175

CPC分类号： H03K19/0005

摘要： An automatic driver adjuster and methods using the same are provided that modify off-chip drivers based on load characteristics. The preferred embodiments are preferably automatic and require little or no human intervention. Preferred embodiments of the current invention analyze and determine the impedance of a node and adjust a number of output drivers in response to the impedance of the node, or analyze a resultant waveform of the node, caused by an input waveform, and adjust a number of output drivers in response to the resultant waveform of the node.

摘要翻译： 提供了一种自动驱动器调节器及其使用方法，其基于负载特性修改片外驱动器。 优选的实施方案优选是自动的，并且需要很少的或不需要人为干预。 本发明的优选实施例分析和确定节点的阻抗并且响应于节点的阻抗调整输出驱动器的数量，或者分析由输入波形引起的节点的合成波形，并且调整多个 输出驱动器响应于该结点的合成波形。

公开(公告)号：US06580650B2

公开(公告)日：2003-06-17

申请号：US09810325

申请日：2001-03-16

申请人： Wayne F. Ellis ,  Russell J. Houghton ,  Mark D. Jacunski ,  Thomas M. Maffitt ,  William R. Tonti

发明人： Wayne F. Ellis ,  Russell J. Houghton ,  Mark D. Jacunski ,  Thomas M. Maffitt ,  William R. Tonti

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C8/08

摘要： A DC analog circuit which monitors a DRAM sample cell access device and outputs a DC reference voltage to the word line voltage regulation system. The resulting output voltage Vpp from the word line voltage regulation system will then vary in accordance with the cell access device parametrics so as to guarantee a full high level will always be written into the DRAM cell.

摘要翻译： DC模拟电路，用于监视DRAM采样单元存取装置，并将直流参考电压输出到字线电压调节系统。 然后，来自字线电压调节系统的结果输出电压Vpp将根据信元接入设备参数而变化，以保证将始终向DRAM单元写入一个完整的高电平。

公开(公告)号：US08345475B2

公开(公告)日：2013-01-01

申请号：US12619771

申请日：2009-11-17

申请人： Chung H. Lam ,  Mark C. H. Lamorey ,  Thomas M. Maffitt

发明人： Chung H. Lam ,  Mark C. H. Lamorey ,  Thomas M. Maffitt

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/10

摘要： One embodiment is a non-volatile memory cell with random access read, program, and erase. The memory cell includes a cell transistor that includes a source region, a drain region, a first insulating spacer, and a second insulating spacer. The memory cell also includes a source-side transistor, a drain-side transistor, a source-side multiplexer, a drain-side multiplexer, a source-side sense amplifier, and a drain-side write driver. A first binary value is stored in a first bit in the memory cell by trapping or releasing a first electric charge in the first insulating spacer. The first bit is read by sensing the resistive change in the cell transistor or by sensing the threshold voltage change in the cell transistor.

摘要翻译： 一个实施例是具有随机访问读取，编程和擦除的非易失性存储单元。 存储单元包括一个单元晶体管，它包括一个源极区，一个漏极区，一个第一绝缘间隔物和一个第二绝缘隔离物。 存储单元还包括源极晶体管，漏极侧晶体管，源极侧多路复用器，漏极侧多路复用器，源极侧读出放大器和漏极侧写入驱动器。 通过在第一绝缘间隔物中捕获或释放第一电荷，将第一二进制值存储在存储器单元中的第一位中。 通过感测单元晶体管中的电阻变化或通过感测单元晶体管中的阈值电压变化来读取第一位。

公开(公告)号：US07778065B2

公开(公告)日：2010-08-17

申请号：US12039990

申请日：2008-02-29

申请人： Mark C. H. Lamorey ,  Thomas M. Maffitt

发明人： Mark C. H. Lamorey ,  Thomas M. Maffitt

IPC分类号： G11C11/00

CPC分类号： G11C13/00 ,  G11C11/1673 ,  G11C11/56 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0054

摘要： An apparatus for sensing the data state of a multiple level, programmable resistive memory device includes an active clamping device connected to a data leg that is selectively coupled a programmable resistive memory element, the clamping device configured to clamp a fixed voltage, at a first node of the data leg, across the memory element, thereby establishing a fixed current sinking capability thereof; and a plurality of differential amplifiers, each of the differential amplifiers configured to compare a first voltage input, taken at a second node of the data leg, with a second voltage input; wherein the second voltage input for each differential amplifier comprises different reference voltages with respect to one another so as to enable each differential amplifier to detect a different resistance threshold, thereby determining a specific resistance state of the programmable resistive memory element.

摘要翻译： 用于感测多级可编程电阻式存储器件的数据状态的装置包括连接到数据支路的有源钳位装置，该有源钳位装置选择性地耦合可编程电阻性存储器元件，钳位装置被配置为在第一节点处钳位固定电压 跨越存储元件，从而建立其固定的电流吸收能力; 以及多个差分放大器，所述差分放大器中的每一个被配置为将在所述数据支路的第二节点处获取的第一电压输入与第二电压输入进行比较; 其中每个差分放大器的第二电压输入包括相对于彼此的不同的参考电压，以使得每个差分放大器能够检测不同的电阻阈值，从而确定可编程电阻式存储器元件的特定电阻状态。

公开(公告)号：US20090282375A1

公开(公告)日：2009-11-12

申请号：US12117784

申请日：2008-05-09

申请人： Nazmul Habib ,  Mark C.H. Lamorey ,  Thomas M. Maffitt ,  Robert McMahon

发明人： Nazmul Habib ,  Mark C.H. Lamorey ,  Thomas M. Maffitt ,  Robert McMahon

IPC分类号： G06F17/50 ,  G01K3/00

CPC分类号： G01K3/14 ,  G01K7/006 ,  G01K7/425

摘要： Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconductor chip. These phase change elements are programmed to have essentially the same amorphous resistance. Temperature-dependent behavior exhibited by each of the phase change elements individually is compared to a reference (e.g., generated by a discrete reference phase change element, generated by another one of the phase change elements, or generated by an external reference) in order to profile the temperature gradient across the semiconductor chip. Once profiled, this temperature gradient can be used to redesign and/or relocate functional cores, to set stress limits for qualification of functional cores and/or to adjust operating specifications of functional cores.

摘要翻译： 公开了一种跨芯片温度感测电路及其相关方法，可用于对片内温度梯度进行分析。 这些实施例结合了大致均匀分布在半导体芯片上的多个相变元件。 这些相变元件被编程为具有基本上相同的无定形电阻。 每个相变元件单独表现出的温度相关行为与参考（例如，由离散参考相变元件产生，由另一个相变元件产生或由外部参考产生）相比较，以便 描述半导体芯片上的温度梯度。 一旦进行了分析，该温度梯度可用于重新设计和/或重新定位功能核心，为功能核心的鉴定和/或调整功能核心的操作规范设定应力限制。

公开(公告)号：US07535783B2

公开(公告)日：2009-05-19

申请号：US11865134

申请日：2007-10-01

申请人： John K. DeBrosse ,  Thomas M. Maffitt ,  Mark C. H. Lamorey

发明人： John K. DeBrosse ,  Thomas M. Maffitt ,  Mark C. H. Lamorey

IPC分类号： G11C7/02

CPC分类号： G11C29/02 ,  G11C7/062 ,  G11C7/067 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/026 ,  G11C29/028 ,  G11C2013/0054

摘要： A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.

摘要翻译： 精密读出放大器装置包括：电流源，被配置为通过参考支路引入可调参考电流; 配置为将参考电流镜像到数据支路的电流镜，所述数据支路选择性地耦合到可编程电阻存储元件; 耦合到所述数据支脚的有源钳位装置，并且被配置为在所述存储元件上钳位固定电压，由此建立其固定的电流吸收能力; 以及差分读出放大器，其具有耦合到所述数据支路的第一输入端和耦合到所述基准支路的第二输入端; 其中每当所述参考电流小于所述存储元件的固定电流吸收能力时，所述差分读出放大器的输出呈现第一逻辑状态，并且每当所述参考电流超过所述固定电流吸收能力时，所述差分读出放大器的输出呈现第二逻辑状态。