公开(公告)号：US20200233980A1

公开(公告)日：2020-07-23

申请号：US16742037

申请日：2020-01-14

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sang-Jae LEE ,  You-Sung KANG ,  Keon-Woo KIM ,  Byoung-Koo KIM ,  Ik-Kyun KIM ,  Ju-Han KIM ,  Tae-Sung KIM ,  Mi-Kyung OH ,  Seung-Yong YOON ,  Seung-Kwang LEE ,  Yong-Sung JEON ,  Doo-Ho CHOI

IPC: G06F21/72 ,  H04L9/32

Abstract: A secret information generation apparatus and a method for operating the secret information generation apparatus. The secret information generation apparatus includes a resistor-capacitor circuit, and a microcontroller unit including a first pin connected to an input terminal of the resistor-capacitor circuit and a second pin connected to an output terminal of the resistor-capacitor circuit, wherein the microcontroller unit is configured to transmit a digital value corresponding to a challenge to the resistor-capacitor circuit through the first pin, receive an output value of the resistor-capacitor circuit corresponding to the digital value through the second pin, convert the received value into a digital value using an analog-to-digital converter, extract one or more valid bits from the converted digital value, and then generate a response.

公开(公告)号：US20230239142A1

公开(公告)日：2023-07-27

申请号：US18155385

申请日：2023-01-17

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Seung-Kwang LEE ,  Do-Young CHUNG ,  Nam-Su JHO

IPC: H04L9/08

CPC classification number: H04L9/0836

Abstract: Disclosed herein is a method for encoding order information. The method may include generating multiple binary trees, preparing multiple different secret keys, determining a binary tree corresponding to any one secret key selected from among the multiple secret keys, and encoding the order information of the determined binary tree.

公开(公告)号：US20150127953A1

公开(公告)日：2015-05-07

申请号：US14250950

申请日：2014-04-11

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Seung-Kwang LEE ,  Doo-Ho CHOI

IPC: G06F21/60 ,  G06F21/55

CPC classification number: G06F21/602

Abstract: Provided is an encoding apparatus including a communication unit configured to receive data from an outside, a memory configured to store an instruction for encoding the data, and a processor configured to encode the data according to the instruction, in which the instruction includes an instruction for encoding the data using a first table for looking up and calculating a result value obtained by encoding according to a predetermined pattern in an a-th round, and when among first to fourth data included in data obtained by encoding through the first table, an i-th bit of exclusive OR of the second to fourth data and a j-th bit of the first data are different, an instruction for encoding the data using a second table for looking up and calculating a result value calculated by performing additional encoding on exclusive OR of the first to fourth data.

Abstract translation: 提供了一种编码装置，包括被配置为从外部接收数据的通信单元，被配置为存储用于对数据进行编码的指令的存储器，以及被配置为根据指令对数据进行编码的处理器，其中该指令包括 使用用于查找的第一表来编码数据，并且计算根据第一轮中的预定模式进行编码获得的结果值，并且当包括在通过第一表编码获得的数据中的第一至第四数据中时，i 第二到第四数据的第二比特和第一数据的第j比特是不同的，使用第二表进行查找和计算通过对排他性进行附加编码而计算出的结果值进行编码的指令 OR为第一至第四数据。

公开(公告)号：US20210390443A1

公开(公告)日：2021-12-16

申请号：US17214588

申请日：2021-03-26

Applicant: Electronics and Telecommunications Research Institute

Inventor： Do-Young CHUNG ,  Doo-Ho CHOI ,  Sok-Joon LEE ,  Seung-Kwang LEE

IPC: G06N10/00 ,  H04L9/06 ,  G06F7/72 ,  H03K19/20

Abstract: Disclosed herein are an apparatus and method for calculating a multiplicative inverse. The apparatus for calculating a multiplicative inverse includes a data input unit for receiving input data, a multiplicative inverse calculation unit for dividing an input degree-8 finite field corresponding to the input data into two first degree-4 finite fields so as to perform Advanced Encryption Standard (AES) encryption on the input data, and for performing a multiplicative inverse calculation on the first degree-4 finite fields in consideration of a circuit depth value (T-Depth) and qubit consumption of quantum gates in a quantum circuit, and a data output unit for outputting result data obtained by performing the multiplicative inverse calculation.

公开(公告)号：US20210058249A1

公开(公告)日：2021-02-25

申请号：US16940146

申请日：2020-07-27

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yong-Sung JEON ,  You-Sung KANG ,  Byoung-Koo KIM ,  Sang-Jae LEE ,  Seung-Kwang LEE ,  Doo-Ho CHOI

IPC: H04L9/08 ,  H04L9/06

Abstract: Disclosed herein are a hardware security module, a device having the hardware security module, and a method for operating the device. The method for verifying integrity of executable code in a device includes dividing, by a Micro-Control Unit (MCU), executable code into multiple blocks, generating, by the MCU, hash values corresponding to the blocks resulting from the division, storing, by a Hardware Security Module (HSM), the generated hash values, calculating, by the MCU, at least one hash value, among hash values of the multiple blocks when the executable code boots, and comparing, by the HSM, the calculated hash value with a hash value corresponding to the calculated hash value, among the hash values stored in the HSM.

公开(公告)号：US20240406209A1

公开(公告)日：2024-12-05

申请号：US18398643

申请日：2023-12-28

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yong-Je CHOI ,  Dae-Won KIM ,  Sang-Su LEE ,  Byeong-Cheol CHOI ,  Seung-Kwang LEE

IPC: H04L9/40

Abstract: Disclosed herein are a method for countering an asynchronous attack on a supply chain security protocol and an apparatus for the same. The method includes, in a supply chain security protocol performed by a terminal device into which a dielet is inserted and an authentication server, performing a self-generation mode in which a counter value within the dielet is registered in the authentication server, performing a read-out mode in which whether an asynchronous attack occurs is detected by comparing the counter values respectively stored in the dielet and the authentication server when a message for communication is sent, and replacing a message for the communication with a random value when an asynchronous attack is detected.

公开(公告)号：US20210152326A1

公开(公告)日：2021-05-20

申请号：US16863232

申请日：2020-04-30

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Seung-Kwang LEE ,  You-Sung KANG ,  Do-Young CHUNG

IPC: H04L9/00 ,  H04L9/06 ,  H03M7/42

Abstract: Disclosed herein are a white-box encryption method for preventing a fault injection attack and an apparatus for the same. The white-box encryption method is configured to acquire a first intermediate value by inputting plaintext to a first part, among all of rounds of a white-box-based encryption algorithm, before table redundancy operations are performed, to input the first intermediate value to a second part for performing the table redundancy operations through at least two lookup tables to which different encodings based on a secret key are applied, among all of the rounds, to acquire a second intermediate value by inputting the output values of the at least two lookup tables to at least one XOR lookup table, and to output ciphertext for the plaintext based on a third part for decoding the second intermediate value.