公开(公告)号：US20230385618A1

公开(公告)日：2023-11-30

申请号：US18307196

申请日：2023-04-26

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kwang IL OH ,  Byung-Do YANG ,  Dongwon LEE ,  Jae-Jin LEE

IPC: G06N3/049 ,  G06N3/063

CPC classification number: G06N3/049 ,  G06N3/063

Abstract: Disclosed is a spike neural network circuit including a synaptic circuit including synapses arranged in rows and columns, an axon circuit that generates a first input spike signal to be provided to a first row among the rows, and a second input spike signal to be provided to a second row among the rows, an input spike detecting circuit that generates an enable signal when detecting a pulse from at least one of the first input spike signal and the second input spike signal, and a first neuron circuit that compares a voltage level of a first accumulated signal, which is output from a first column among the columns, with a threshold voltage level in response to the enable signal, and outputs a first output spike signal when the voltage level of the first accumulated signal exceeds the threshold voltage level.

公开(公告)号：US20230385620A1

公开(公告)日：2023-11-30

申请号：US18125553

申请日：2023-03-23

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kwang IL OH ,  Byung-Do YANG ,  Dongwon LEE ,  Jae-Jin LEE

IPC: G06N3/063 ,  G06N3/049

CPC classification number: G06N3/063 ,  G06N3/049

Abstract: Disclosed is a spike neural network circuit which includes a pulse generator that receives an input spike signal and generates a first modulation pulse and a second modulation pulse based on the input spike signal, first and second current source arrays controlled based on a weight memory, a membrane capacitor, a first switch that delivers a first calculation signal generated from the first current source array to the membrane capacitor, in response to the first modulation pulse, and a second switch that delivers a second calculation signal generated from the second current source array to the membrane capacitor, in response to the second modulation pulse.

公开(公告)号：US20230385616A1

公开(公告)日：2023-11-30

申请号：US18125552

申请日：2023-03-23

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kwang IL OH ,  Byung-Do YANG ,  Dongwon LEE ,  Jae-Jin LEE

IPC: G06N3/049 ,  G06N3/063

CPC classification number: G06N3/049 ,  G06N3/063

Abstract: Disclosed is a spike neural network circuit including a weight storage that receives an input spike signal and outputs data based on a weight, a charge sharing synaptic circuit that generates a synaptic voltage based on the output data, a switched capacitor circuit that naturally discharges the generated synaptic voltage, a voltage-to-current conversion circuit that receives the synaptic voltage and generates a membrane voltage, and a neuron circuit that receives the membrane voltage and a threshold voltage and generates an output spike signal based on the received membrane voltage and the received threshold voltage.