公开(公告)号：US20140351828A1

公开(公告)日：2014-11-27

申请号：US14258806

申请日：2014-04-22

Applicant: Electronics and Telecommunications Research Institute

Inventor： Yoo-Kyoung LEE ,  Kyung-Jin BYUN ,  Nak-Woong EUM

IPC: G06F9/48

CPC classification number: G06F9/4812 ,  Y02D10/24

Abstract: An apparatus and method for controlling a multi-core SoC including a main core and at least one sub-core are disclosed. The apparatus includes a determination unit, a storage unit, and a control unit. The determination unit determines whether or not to drive the sub-core by taking the performance or power of the multi-core SoC into consideration. The storage unit stores state information including a register of the main core or the sub-core in accordance with a determination of the determination unit. The control unit performs control so that the main core and the sub-core execute a sub-task, that is, a task of the sub-core, through exchange by sharing the state information.

Abstract translation: 公开了一种用于控制包括主芯和至少一个子芯的多芯SoC的装置和方法。 该装置包括确定单元，存储单元和控制单元。 确定单元通过考虑多核SoC的性能或能力来确定是否驱动子核心。 存储单元根据确定单元的确定存储包括主核或子核的寄存器的状态信息。 控制单元进行控制，使得主核和子核通过共享状态信息进行交换来执行子任务，即子核的任务。

公开(公告)号：US20130216145A1

公开(公告)日：2013-08-22

申请号：US13675616

申请日：2012-11-13

Applicant: Electronics and Telecommunications Research Institute

Inventor： Yoo-Kyoung LEE ,  Nak Woong Eum ,  Hee-Bum Jung

IPC: G06T1/60 ,  G06T9/00

CPC classification number: G06T1/60 ,  G06F13/00 ,  G06F16/00 ,  G06T9/00 ,  H04L49/00 ,  H04L51/10 ,  H04L51/18 ,  H04N1/2137

Abstract: Disclosed is an apparatus for processing an image data including: a CPU, a system memory connected with the CPU through a system bus, a communication packet processing unit configured to receive packet data from an external network, and a cut through memory configured to be connected with the communication packet processing unit through the system bus and a cut through memory bus and include a cut through memory storing the received packet data.

Abstract translation: 公开了一种处理图像数据的装置，包括：CPU，通过系统总线与CPU连接的系统存储器，被配置为从外部网络接收分组数据的通信分组处理单元，以及被配置为连接的切换存储器 通过通信分组处理单元通过系统总线和切断的存储器总线，并且包括存储接收的分组数据的切入存储器。