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1.发明授权Circuit design optimization of integrated circuit based clock gated memory elements 有权基于集成电路的时钟门控存储器元件的电路设计优化公开(公告)号：US07676778B2
公开(公告)日：2010-03-09
申请号：US11773412
申请日：2007-07-04
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A novel method for optimizing the design of digital circuits containing clock gated memory elements. The method unclock gates memory elements by adding necessary feedback loops. Logic functions of memory element outputs in the circuit are viewed as a whole, rather than as separate functions for each input. Detection of duplicate unclock gated memory elements is then effected by identifying identical canonical representations of said unclock gated memory elements. Identified duplicate clock gated memory elements can then be eliminated from the original digital circuit. Further optimization can be accomplished by applying standard logic optimization algorithms to all unclock gated memory elements in said digital circuit. The resulting optimized circuit is clock gated and replaces the original clock gated circuit in said digital circuit.
摘要翻译： 一种用于优化包含时钟门控存储器元件的数字电路设计的新颖方法。 该方法通过添加必要的反馈环来解锁门存储器元件。 电路中存储元件输出的逻辑功能作为一个整体来看待，而不是作为每个输入的独立功能。 然后通过识别所述非锁定门控存储器元件的相同规范表示来检测重复的非锁定门控存储器元件。 然后可以从原始数字电路中消除识别的重复时钟门控存储器元件。 可以通过将标准逻辑优化算法应用于所述数字电路中的所有非锁定门控存储器元件来实现进一步优化。 所得到的优化电路是时钟门控，并替代所述数字电路中的原始时钟门控电路。
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2.发明申请CIRCUIT DESIGN OPTIMIZATION OF INTEGRATED CIRCUIT BASED CLOCK GATED MEMORY ELEMENTS 有权基于集成电路的时钟选择存储元件的电路设计优化公开(公告)号：US20090013289A1
公开(公告)日：2009-01-08
申请号：US11773412
申请日：2007-07-04
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A novel method for optimizing the design of digital circuits containing clock gated memory elements. The method unclock gates memory elements by adding necessary feedback loops. Logic functions of memory element outputs in the circuit are viewed as a whole, rather than as separate functions for each input. Detection of duplicate unclock gated memory elements is then effected by identifying identical danonical representations of said unclock gated memory elements. Identified duplicate clock gated memory elements can then be eliminated from the original digital circuit. Further optimization can be accomplished by applying standard logic optimization algorithms to all unclock gated memory elements in said digital circuit. The resulting optimized circuit is clock gated and replaces the original clock gated circuit in said digital circuit.
摘要翻译： 一种用于优化包含时钟门控存储器元件的数字电路设计的新颖方法。 该方法通过添加必要的反馈环来解锁门存储器元件。 电路中存储元件输出的逻辑功能作为一个整体来看待，而不是作为每个输入的独立功能。 然后通过识别所述非锁定门控存储器元件的相同的丹参表示来检测重复的非锁定门控存储器元件。 然后可以从原始数字电路中消除识别的重复时钟门控存储器元件。 可以通过将标准逻辑优化算法应用于所述数字电路中的所有非锁定门控存储器元件来实现进一步优化。 所得到的优化电路是时钟门控，并替代所述数字电路中的原始时钟门控电路。
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公开(公告)号：US07458050B1
公开(公告)日：2008-11-25
申请号：US12053384
申请日：2008-03-21
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method to cluster Boolean functions for clock gating according to various exemplary embodiments can include identifying at least two small gating groups within a clock tree representative of an electrical network and at least two gating functions of the at least two small gating groups, wherein the at least two gating functions are Boolean functions; performing hierarchical clustering on the at least two gating functions using a similarity measure that describes a distance between the at least two gating functions such that the clustering forms a merge function of a cluster generated and displayed in a form of a dendrogram; assigning to each gating domain a merit value according to a power consumption profile of the gating domain using a merit function; and partitioning the cluster into gating groups using the dendrogram to construct a directed acyclic graph to determine a partition which maximize the overall power saving.
摘要翻译： 根据各种示例性实施例的用于对用于时钟门控的布尔函数进行聚类的方法可以包括识别表示电网的时钟树内的至少两个小门控组和至少两个小门控组的至少两个门控功能，其中at 最少两个门控函数是布尔函数; 使用描述所述至少两个门控功能之间的距离的相似度测量来对所述至少两个门控功能执行分级聚类，使得所述聚类形成以树形图形式生成和显示的聚类的合并功能; 根据使用优点函数的门控域的功耗曲线，向每个选通域分配优值; 并使用树形图将群集分成选通组，以构建有向无环图，以确定最大化整体节能的分区。
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公开(公告)号：US07562325B1
公开(公告)日：2009-07-14
申请号：US12236543
申请日：2008-09-24
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A system for clustering Boolean functions for clock gating according to various exemplary embodiments can include a computer configured to identify at least two small gating groups within a clock tree representative of an electrical network and at least two gating functions of the at least two small gating groups, wherein the at least two gating functions are Boolean functions; perform hierarchical clustering on the at least two gating functions using a similarity measure that describes a distance between the at least two gating functions such that the clustering forms a merge function of a cluster generated and displayed in a form of a dendrogram; assign to each gating domain a merit value according to a power consumption profile of the gating domain using a merit function; and partition the cluster into gating groups using the dendrogram to construct a directed acyclic graph to determine a partition which maximize the overall power saving.
摘要翻译： 根据各种示例性实施例的用于对用于时钟选通的布尔函数进行聚类的系统可以包括计算机，其被配置为识别表示电网的时钟树内的至少两个小门控组，以及至少两个小选通组的至少两个门控功能 ，其中所述至少两个门控函数是布尔函数; 使用描述所述至少两个门控功能之间的距离的相似度测量来对所述至少两个门控功能执行层次聚类，使得所述聚类形成以树形图形式生成和显示的聚类的合并功能; 根据使用优点函数的门控域的功耗曲线，向每个选通域分配优值; 并使用树形图将群集分成门控组，以构建有向无环图，以确定最大化整体节能的分区。
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公开(公告)号：US20130007683A1
公开(公告)日：2013-01-03
申请号：US13175854
申请日：2011-07-03
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/14
摘要： A method, apparatus and computer program product for modifying a circuit design. The method comprising: obtaining a design of a circuit, the design comprising at least a first memory element and a second memory element. The method further comprising selecting the second memory element to be a dominant memory element over the first memory element. The method further comprising modifying the design of the circuit by replacing usage of an output signal of the first memory element with usage of an output signal of the dominant memory element in one or more cycles in which values of the output signals of the first memory element and the dominant memory element are equal. Whereby a reduction in observabiltiy of the first memory element in the design is achieved.
摘要翻译： 一种用于修改电路设计的方法，装置和计算机程序产品。 该方法包括：获得电路的设计，该设计包括至少第一存储器元件和第二存储器元件。 所述方法还包括：通过所述第一存储器元件选择所述第二存储器元件作为主要存储器元件。 该方法还包括通过在一个或多个周期内替换使用主存储器元件的输出信号的第一存储元件的输出信号的使用来替换电路的设计，其中第一存储元件的输出信号的值 而显存存储元件相等。 从而实现了设计中第一个存储元件的可观察性的减少。
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公开(公告)号：US08539403B2
公开(公告)日：2013-09-17
申请号：US13175854
申请日：2011-07-03
IPC分类号： G06F9/455
CPC分类号： G06F17/505 , G06F2217/14
摘要： A method, apparatus and computer program product for modifying a circuit design. The method comprising: obtaining a design of a circuit, the design comprising at least a first memory element and a second memory element. The method further comprising selecting the second memory element to be a dominant memory element over the first memory element. The method further comprising modifying the design of the circuit by replacing usage of an output signal of the first memory element with usage of an output signal of the dominant memory element in one or more cycles in which values of the output signals of the first memory element and the dominant memory element are equal. Whereby a reduction in observabiltiy of the first memory element in the design is achieved.
摘要翻译： 一种用于修改电路设计的方法，装置和计算机程序产品。 该方法包括：获得电路的设计，该设计包括至少第一存储器元件和第二存储器元件。 所述方法还包括：通过所述第一存储器元件选择所述第二存储器元件作为主要存储器元件。 该方法还包括通过在一个或多个周期内替换使用主存储器元件的输出信号的第一存储元件的输出信号的使用来替换电路的设计，其中第一存储元件的输出信号的值 而显存存储元件相等。 从而实现了设计中第一个存储元件的可观察性的减少。
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公开(公告)号：US07484187B2
公开(公告)日：2009-01-27
申请号：US11295936
申请日：2005-12-07
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Given a function F of a circuit having a data latching device and a feedback loop feeding an output Q of the device into logic which feeds the device, a method includes extracting at least one data independent case and clock-gating the device with the at least one data independent case. The method also includes eliminating the feedback loop if function F depends only on Q with a positive polarity or leaving the feedback loop if function F depends on Q in both positive and negative polarities.
摘要翻译： 给定具有数据锁存装置的电路的功能F和将装置的输出端Q馈送给装置的逻辑的反馈环路，一种方法包括提取至少一个与数据无关的情况，并且至少具有至少一个数据锁定装置的时钟选通装置 一个数据独立的情况。 该方法还包括消除反馈回路，如果功能F仅取决于具有正极性的Q或离开反馈回路，如果功能F取决于正极和负极性的Q。
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公开(公告)号：US07853907B2
公开(公告)日：2010-12-14
申请号：US11836160
申请日：2007-08-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： A novel method for optimizing the implementation of clock gating logic in digital circuits utilizing clock gating. The method over-approximates the clock gating function by removing the variable with the least influence on the resulting approximation function. Approximations of clock gating functions expressed in normal form are performed by removing an appropriate component from the function. Approximations of clock gating functions expressed in conjunctive normal form are performed by removing a clause from the function. Approximations of clock gating functions expressed in disjunctive normal form are performed by removing a literal from a clause in the function.
摘要翻译： 一种利用时钟门控优化数字电路中时钟门控逻辑实现的新方法。 该方法通过去除对最终近似函数影响最小的变量来过滤近似时钟门控功能。 以正常形式表示的时钟门控功能的近似通过从功能中移除适当的组件来执行。 以连续正常形式表示的时钟门控函数近似通过从函数中删除子句来执行。 以分离正常形式表示的时钟门控功能的近似通过从函数中的子句中删除文字来执行。
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公开(公告)号：US20090044154A1
公开(公告)日：2009-02-12
申请号：US11836160
申请日：2007-08-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： A novel method for optimizing the implementation of clock gating logic in digital circuits utilizing clock gating. The method over-approximates the clock gating function by removing the variable with the least influence on the resulting approximation function. Approximations of clock gating functions expressed in normal form are performed by removing an appropriate component from the function. Approximations of clock gating functions expressed in conjunctive normal form are performed by removing a clause from the function. Approximations of clock gating functions expressed in disjunctive normal form are performed by removing a literal from a clause in the function.
摘要翻译： 一种利用时钟门控优化数字电路中时钟门控逻辑实现的新方法。 该方法通过去除对最终近似函数影响最小的变量来过滤近似时钟门控功能。 以正常形式表示的时钟门控功能的近似通过从功能中移除适当的组件来执行。 以连续正常形式表示的时钟门控函数近似通过从函数中删除子句来执行。 以分离正常形式表示的时钟门控功能的近似通过从函数中的子句中删除文字来执行。
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10.发明申请APPARATUS FOR AND METHOD OF ESTIMATING THE QUALITY OF CLOCK GATING SOLUTIONS FOR INTEGRATED CIRCUIT DESIGN 审中-公开用于集成电路设计的时钟增益解决方案的质量估算方法公开(公告)号：US20080301604A1
公开(公告)日：2008-12-04
申请号：US11755015
申请日：2007-05-30
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5022 , G06F2217/62
摘要： A novel apparatus for and method of estimating the quality of candidate clock gating solutions. The quality estimation mechanism of the present invention filters candidate clock gating solutions by estimating a measure of the quality of each candidate solution. The effect of the proposed solution on both timing and leakage power is considered by determining the intersection coefficient for each candidate clock gating solution. The intersection coefficient (IC) is the number of signals shared by both the data logic portion and clock enable logic portions of a proposed clock gating solution. Only those proposed solutions whose IC value is less than or equal to a threshold are considered as possible clock gating solutions. The IC value functions as a reliable predictor of whether a candidate clock gating solution is a good solution without requiring complex heavy analyses that would normally be applied to the final circuit design.
摘要翻译： 一种用于估计候选时钟门控解决方案质量的新颖设备和方法。 本发明的质量估计机制通过估计每个候选解决方案的质量的度量来对候选时钟门控解决方案进行滤波。 通过确定每个候选时钟门控解决方案的交点系数来考虑所提出的解决方案对定时和漏电功率的影响。 相交系数（IC）是所提出的时钟门控解决方案的数据逻辑部分和时钟使能逻辑部分共享的信号数。 只有IC值小于或等于阈值的提出的解决方案被认为是可能的时钟门控解决方案。 IC值作为候选时钟门控解决方案是否是一个很好的解决方案的可靠预测器，而不需要通常应用于最终电路设计的复杂的重分析。
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