Method of fabricating reduced subthreshold leakage current submicron NFET's with high III/V ratio material
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    发明申请
    Method of fabricating reduced subthreshold leakage current submicron NFET's with high III/V ratio material 审中-公开
    制造具有高III / V比材料的亚阈值漏电流亚微米NFET的方法

    公开(公告)号:US20070138507A1

    公开(公告)日:2007-06-21

    申请号:US11303776

    申请日:2005-12-16

    IPC分类号: H01L29/739

    CPC分类号: H01L29/7784

    摘要: A method of fabricating an enhancement mode semiconductor device comprises providing a compound semiconductor substrate, epitaxially growing on the substrate a first portion of a buffer, the first portion including gallium arsenide (GaAs), growing a second portion of the buffer, the second portion including a high V/III ratio and high aluminum (Al) mole fraction aluminum gallium arsenide (AlGaAs), and epitaxially growing a stack of compound semiconductor layers on the buffer. An enhancement mode semiconductor device is then formed in the stack.

    摘要翻译: 一种制造增强型半导体器件的方法包括提供化合物半导体衬底,在衬底上外延生长缓冲器的第一部分,第一部分包括砷化镓(GaAs),生长缓冲器的第二部分,第二部分包括 高V / III比和高铝(Al)摩尔分数的砷化镓铝(AlGaAs),并且在缓冲器上外延生长一叠化合物半导体层。 然后在堆叠中形成增强型半导体器件。