摘要:
Disclosed herein is a reconfigurable mixed signal distributed arithmetic system including: an array of tunable voltage references operable for receiving a delayed digital input signal; a combination device in electrical communication with the array of tunable floating-gate voltage references that selectively combines an output of the array of tunable voltage references into an analog output signal; and a feedback element in electrical communication with the combination device, wherein the array of tunable voltages and the delayed digital input signal combine to perform a distributed arithmetic function and the reconfigurable mixed signal distributed arithmetic system responsively generates the analog output signal.
摘要:
Systems and methods for very high throughput adaptive filtering using distributed arithmetic are disclosed. One distributed arithmetic adaptive filter may include a memory for storing a first and second lookup table. The first lookup table may include 2K filter weights addressed by the rightmost bits of each of K signal samples stored in a plurality of registers. The filter may include a controller configured to update the second lookup table with each possible combination of the sums of the K most recent input samples and update each of the 2K filter weights of the first lookup table based on the combination of the sums of the K most recent input samples stored in the second lookup table. The second lookup-table may be updated during a filtering operation that uses the first lookup-table. One filter may include a plurality of sub-filters with each sub-filter having first and second lookup tables.