公开(公告)号：US06537895B1

公开(公告)日：2003-03-25

申请号：US09713513

申请日：2000-11-14

申请人： Eric R. Miller ,  Stephen R. Moon

发明人： Eric R. Miller ,  Stephen R. Moon

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  Y10S438/973

摘要： A method of forming a shallow trench isolation region in a silicon wafer which results in the elimination of long range slip dislocations in the wafer and reduces leakage current across the isolation regions. Long shallow trenches are formed in a silicon wafer at a 45 degree angle to the (111) plane of the wafer. This is achieved by moving the primary flat of the wafer to the (100) plane prior to the formation of the trenches, which causes the bottom edges of the long trenches to intersect with several (111) planes, so that stresses do not propagate along any one single (111) plane. The trenches are then filled with an insulative material, such as oxide.

摘要翻译： 一种在硅晶片中形成浅沟槽隔离区域的方法，其导致消除晶片中的长距离滑移位错并且减少跨越隔离区域的漏电流。 在硅晶片中以与晶片的（111）平面成45度的角度形成长的浅沟槽。 这通过在形成沟槽之前将晶片的主平面移动到（100）平面来实现，这导致长沟槽的底部边缘与几个（111）平面相交，使得应力不沿着 任何一个单（111）平面。 然后用绝缘材料（例如氧化物）填充沟槽。