公开(公告)号：US09965430B2

公开(公告)日：2018-05-08

申请号：US15001196

申请日：2016-01-19

Applicant: Faraday Technology Corp.

Inventor： Yuan-Min Hu ,  Yin-Fu Lin ,  Shan-Chih Wen

IPC: G06F13/00 ,  G06F13/40

CPC classification number: G06F13/4068

Abstract: An integrated circuit and an operation method of a SERDES PHY layer circuit thereof are provided. When the SERDES PHY layer circuit is in a calibration preparation state and a signal of a first calibration input pin is an enable state, or when the SERDES PHY layer circuit is in the calibration preparation state, and signals of first and second calibration input pins are in the enable state, the SERDES PHY layer circuit enters a calibration state (using a reference resistor for current calibration). After the current calibration is completed, the SERDES PHY layer circuit enters a calibration completion state (without using the reference resistor and connecting the first calibration input pin to the first calibration output pin). The SERDES PHY layer circuit sets the signal of the first calibration output pin to a disable state when the SERDES PHY layer circuit is not in the calibration completion state.

公开(公告)号：US20170154002A1

公开(公告)日：2017-06-01

申请号：US15001196

申请日：2016-01-19

Applicant: Faraday Technology Corp.

Inventor： Yuan-Min Hu ,  Yin-Fu Lin ,  Shan-Chih Wen

IPC: G06F13/40

CPC classification number: G06F13/4068

Abstract: An integrated circuit and an operation method of a SERDES PHY layer circuit thereof are provided. When the SERDES PHY layer circuit is in a calibration preparation state and a signal of a first calibration input pin is an enable state, or when the SERDES PHY layer circuit is in the calibration preparation state, and signals of first and second calibration input pins are in the enable state, the SERDES PHY layer circuit enters a calibration state (using a reference resistor for current calibration). After the current calibration is completed, the SERDES PHY layer circuit enters a calibration completion state (without using the reference resistor and connecting the first calibration input pin to the first calibration output pin). The SERDES PHY layer circuit sets the signal of the first calibration output pin to a disable state when the SERDES PHY layer circuit is not in the calibration completion state.