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25 条记录 (耗时 0.038 秒)

    Data recording/reproducing apparatus having viterbi decoder and method thereof
    7.
    发明授权
    Data recording/reproducing apparatus having viterbi decoder and method thereof 失效
    具有维特比解码器的数据记录/再现装置及其方法

    公开(公告)号：US5659309A

    公开(公告)日：1997-08-19

    申请号：US389773

    申请日：1995-02-16

    申请人： Terumi Takashi ,  Yasuhide Ouchi ,  Seiichi Mita ,  Akihiko Hirano ,  Naoki Satoh

    发明人： Terumi Takashi ,  Yasuhide Ouchi ,  Seiichi Mita ,  Akihiko Hirano ,  Naoki Satoh

    IPC分类号： G11B20/18 ,  G11B20/10 ,  H03M13/23 ,  H03M13/41 ,  H03M7/00

    CPC分类号： H03M13/6343 ,  G11B20/10009 ,  H03M13/41

    摘要： A data recording/reproducing apparatus and method therefor having a Viterbi decoder which stores operation result values of an inputted reproduced signal and the reference value when the peak value of the reproduced signal is updated, compares this value with the reproduced signal in amplitude, updates the stored value when the result satisfies the predetermined condition, detects a change in the polarity of the comparison result, controls the clock counter depending on the status of the peak value updating signal, sets 1 in the shift register at the position indicated by the counter according to the detected polarity inversion signal when the peak value is updated, and accordingly makes the updating and detecting operations independent of operations of addition and subtraction of the current reproduced signal and reference value and operations of addition and subtraction of amplitude comparison.

    摘要翻译： 一种数据记录/再现装置和方法，其具有维特比解码器，其在再现信号的峰值被更新时存储输入的再现信号的运算结果值和参考值，将该值与振幅的再现信号进行比较，更新 当结果满足预定条件时，存储值检测比较结果的极性的变化，根据峰值更新信号的状态来控制时钟计数器，根据计数器指示的位置在移位寄存器中设置1 当更新峰值时检测到的极性反转信号，并且因此使得更新和检测操作与当前再现信号的加法和减法操作无关，参考值和幅度比较的相加和减法操作。

    Method for error correction and circuit for realizing same
    10.
    发明授权
    Method for error correction and circuit for realizing same 失效
    误差校正方法及其实现方法

    公开(公告)号：US5325364A

    公开(公告)日：1994-06-28

    申请号：US412514

    申请日：1989-09-26

    申请人： Yasuhide Ouchi ,  Hajime Aoi ,  Yoshihisa Kamo ,  Yosuke Seo ,  Hitoshi Kakuta

    发明人： Yasuhide Ouchi ,  Hajime Aoi ,  Yoshihisa Kamo ,  Yosuke Seo ,  Hitoshi Kakuta

    IPC分类号： G06F11/10 ,  G06F11/14 ,  H03M13/00 ,  G06F11/00

    CPC分类号： G06F11/1076 ,  G06F11/1008 ,  G06F11/1443

    摘要： An error correction circuit which includes a specification circuit for specifying erroneous portions in a first data set reproduced from a recording medium, a register for storing the reproduced first data set including the erroneous portions thus specified and a reproducing circuit responsive to the reproduced first data set for reproducing again the first data set from the recording medium to obtain retry data, when there exist erroneous portions in the reproduced first data set stored in the register. The correction circuit also includes a data replace circuit, connected to receive the retry data, for replacing information at the specified erroneous portions in the reproduced first data set stored in the register by information at corresponding portions in the retry data.

    摘要翻译： 一种误差校正电路，包括用于指定从记录介质再现的第一数据组中的错误部分的指定电路，用于存储包括如此指定的错误部分的再现的第一数据组的寄存器和响应于再现的第一数据集的再现电路 当存储在寄存器中的再现的第一数据组中存在错误部分时，再次从记录介质再现第一数据组以获得重试数据。 校正电路还包括连接以接收重试数据的数据替换电路，用于通过重试数据中的相应部分处的信息替换存储在寄存器中的再现的第一数据集中的指定错误部分处的信息。