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公开(公告)号：US20220180923A1
公开(公告)日：2022-06-09
申请号：US17110674
申请日：2020-12-03
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor： Akhilesh R. JAISWAL , Bipul C. PAUL , Steven R. SOSS
IPC: G11C11/412 , G11C11/419
Abstract: The present disclosure relates to a structure including a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.
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