公开(公告)号：US20200117696A1

公开(公告)日：2020-04-16

申请号：US16159450

申请日：2018-10-12

Applicant: Google LLC

Inventor： Anand Suresh Kane ,  Ravi Narayanaswami

IPC: G06F17/10 ,  G06F7/485 ,  G06F7/50 ,  G06N3/063

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a circuit configured to add multiple inputs. The circuit includes a first adder section that receives a first input and a second input and adds the inputs to generate a first sum. The circuit also includes a second adder section that receives the first and second inputs and adds the inputs to generate a second sum. An input processor of the circuit receives the first and second inputs, determines whether a relationship between the first and second inputs satisfies a set of conditions, and selects a high-power mode of the adder circuit or a low-power mode of the adder circuit using the determined relationship between the first and second inputs. The high-power mode is selected and the first and second inputs are routed to the second adder section when the relationship satisfies the set of conditions.

公开(公告)号：US20210019361A1

公开(公告)日：2021-01-21

申请号：US17063813

申请日：2020-10-06

Applicant: Google LLC

Inventor： Anand Suresh Kane ,  Ravi Narayanaswami

IPC: G06F17/10 ,  G06F7/485 ,  G06F7/50 ,  G06N3/063

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a circuit configured to add multiple inputs. The circuit includes a first adder section that receives a first input and a second input and adds the inputs to generate a first sum. The circuit also includes a second adder section that receives the first and second inputs and adds the inputs to generate a second sum. An input processor of the circuit receives the first and second inputs, determines whether a relationship between the first and second inputs satisfies a set of conditions, and selects a high-power mode of the adder circuit or a low-power mode of the adder circuit using the determined relationship between the first and second inputs. The high-power mode is selected and the first and second inputs are routed to the second adder section when the relationship satisfies the set of conditions.

公开(公告)号：US10824692B2

公开(公告)日：2020-11-03

申请号：US16159450

申请日：2018-10-12

Applicant: Google LLC

Inventor： Anand Suresh Kane ,  Ravi Narayanaswami

IPC: G06F7/485 ,  G06F17/10 ,  G06F7/50 ,  G06N3/063

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a circuit configured to add multiple inputs. The circuit includes a first adder section that receives a first input and a second input and adds the inputs to generate a first sum. The circuit also includes a second adder section that receives the first and second inputs and adds the inputs to generate a second sum. An input processor of the circuit receives the first and second inputs, determines whether a relationship between the first and second inputs satisfies a set of conditions, and selects a high-power mode of the adder circuit or a low-power mode of the adder circuit using the determined relationship between the first and second inputs. The high-power mode is selected and the first and second inputs are routed to the second adder section when the relationship satisfies the set of conditions.

公开(公告)号：US11586701B2

公开(公告)日：2023-02-21

申请号：US17063813

申请日：2020-10-06

Applicant: Google LLC

Inventor： Anand Suresh Kane ,  Ravi Narayanaswami

IPC: G06F7/485 ,  G06F17/10 ,  G06F7/50 ,  G06N3/063

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a circuit configured to add multiple inputs. The circuit includes a first adder section that receives a first input and a second input and adds the inputs to generate a first sum. The circuit also includes a second adder section that receives the first and second inputs and adds the inputs to generate a second sum. An input processor of the circuit receives the first and second inputs, determines whether a relationship between the first and second inputs satisfies a set of conditions, and selects a high-power mode of the adder circuit or a low-power mode of the adder circuit using the determined relationship between the first and second inputs. The high-power mode is selected and the first and second inputs are routed to the second adder section when the relationship satisfies the set of conditions.