公开(公告)号：US20250093921A1

公开(公告)日：2025-03-20

申请号：US18559378

申请日：2022-11-18

Applicant: Google LLC

Inventor： Syed Shakir Iqbal ,  Vaibhav Gupta

IPC: G06F1/24 ,  G06F1/12

Abstract: A method of resetting a number of functional components in a computing device includes determining a number of cycles required to reset the functional components based on a predetermined voltage controlling a reset synchronizer to run for the determined number of cycles wherein the reset synchronizer controls a reset network connected to the functional components, and wherein the determined number of cycles at a first voltage is different than a determined number of cycles at a second voltage.

公开(公告)号：US20250076380A1

公开(公告)日：2025-03-06

申请号：US18726670

申请日：2022-01-05

Applicant: Google LLC

Inventor： Syed Shakir Iqbal

IPC: G01R31/3185

Abstract: Methods, systems, and apparatus, for a high throughput scan architecture. The scan architecture can include a clock controller, a decompressor, a scan chain, and a compressor. In some implementations, a set of values that represents a particular data pattern is received. A first data signal is generated using at least a portion of the values in the set of values, where the first data signal has a first frequency. A first series of latches and a second series of latches are used to extract alternating values of the at least portion of values from the first data signal, where the first series and second series of latches extract the alternating values at a second frequency that is a fraction of the first frequency. Outputs of the first and second series of latches are combined to generate a second data signal, where the second data signal has the first frequency.

公开(公告)号：US12028067B2

公开(公告)日：2024-07-02

申请号：US17757926

申请日：2021-06-21

Applicant: Google LLC

Inventor： Syed Shakir Iqbal

IPC: H03K19/23 ,  H03K19/003

CPC classification number: H03K19/23 ,  H03K19/003

Abstract: The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit includes a data storage element to store a data value, another data storage element to store a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element) to store both the data value and the complementary data value, and voting logic that may enable a complementary data storage scheme with inter-circuit redundancy to prevent SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.

公开(公告)号：US20240305300A1

公开(公告)日：2024-09-12

申请号：US18665265

申请日：2024-05-15

Applicant: Google LLC

Inventor： Syed Shakir Iqbal

IPC: H03K19/23 ,  H03K19/003

CPC classification number: H03K19/23 ,  H03K19/003

Abstract: The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit includes a data storage element to store a data value, another data storage element to store a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element) to store both the data value and the complementary data value, and voting logic that may enable a complementary data storage scheme with inter-circuit redundancy to prevent SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.

公开(公告)号：US20240171179A1

公开(公告)日：2024-05-23

申请号：US17757926

申请日：2021-06-21

Applicant: Google LLC

Inventor： Syed Shakir Iqbal

IPC: H03K19/23 ,  H03K19/003

CPC classification number: H03K19/23 ,  H03K19/003

Abstract: The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit includes a data storage element to store a data value, another data storage element to store a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element to store both the data value and the complementary data value, and voting logic that may enable a complementary data storage scheme with inter-circuit redundancy to prevent SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.