公开(公告)号：US20240242677A1

公开(公告)日：2024-07-18

申请号：US18269704

申请日：2023-01-04

Applicant: HONOR DEVICE CO., LTD.

Inventor： Linhong HAN ,  Wanming WU ,  Di GENG ,  Ling LI ,  Zheng TIAN

IPC: G09G3/3266 ,  G09G3/3225 ,  G11C19/28

CPC classification number: G09G3/3266 ,  G09G3/3225 ,  G11C19/28 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2330/021

Abstract: This application provides a shift register, a gate drive circuit, a display panel, and an electronic device. The shift register includes a node control module, electrically connected to a first level signal receiving end, a second level signal receiving end, a first node, and a second node; an input module, electrically connected to a first clock signal end, a trigger signal input end, and the second node; an output module, electrically connected to the first level signal receiving end, the second level signal receiving end, the first node, a third node, and a drive signal output end; a first voltage stabilizing module, electrically connected to the first node, a fourth node, and the second level signal receiving end; and a second voltage stabilizing module, electrically connected to the second node, the third node, the fourth node, and a second clock signal end.

公开(公告)号：US20240379064A1

公开(公告)日：2024-11-14

申请号：US18271467

申请日：2023-01-04

Applicant: Honor Device Co., Ltd.

Inventor： Linhong HAN ,  Wanming WU ,  Di GENG ,  Ling LI ,  Zheng TIAN

IPC: G09G3/3266 ,  G09G3/3233 ,  G11C19/28

Abstract: This application provides a shift register, a gate drive circuit, a display panel, and an electronic device. The shift register includes: a node control module, electrically connected to a first level signal receive end that receives a low level, a second level signal receive end that receives a high level, a first clock signal end, a second clock signal end, a first node, and a second node; an input module, electrically connected to the second clock signal end, a trigger signal input end, and the second node; a voltage regulator module, electrically connected to the second node, a third node, and the second clock signal end; and an output module, electrically connected to the first level signal receive end, the second level signal receive end, a drive signal output end, the first node, and the third node.