Integrated circuit die and manufacture method thereof

    公开(公告)号:US10607913B2

    公开(公告)日:2020-03-31

    申请号:US15797549

    申请日:2017-10-30

    Abstract: The present invention provide an IC die, including an underlay; an active component; an interconnection layer, covering the active component, where the interconnection layer includes multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers includes metal cabling and a metal welding pad; and a heat dissipation layer, where the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer includes a plastic packaging material, and the heat dissipation layer includes an electrical-insulating material whose heat conductivity is greater than a preset value.

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