Multiplication Circuit, System on Chip, and Electronic Device

    公开(公告)号:US20200218509A1

    公开(公告)日:2020-07-09

    申请号:US16822720

    申请日:2020-03-18

    Abstract: A multiplication circuit is provided, the circuit is configured to perform a multiplication operation on two pieces of data: A and B, and includes: an addition subcircuit configured to obtain logarithmic field data a and b that corresponding to A and B, and perform an addition operation on a and b to obtain c, where c includes an integral part and a fractional part; an exponentiation operation subcircuit configured to perform an exponentiation operation in which a base is 2 and an exponent is the fractional part of c, to obtain an exponentiation operation result; a shift subcircuit configured to shift the exponentiation operation result based on the integral part of c to obtain a shift result; and an output subcircuit, configured to output a product of A and B based on signs of a and b and with reference to the shift result.

    Method, circuit, and SOC for performing matrix multiplication operation

    公开(公告)号:US11860970B2

    公开(公告)日:2024-01-02

    申请号:US17841162

    申请日:2022-06-15

    CPC classification number: G06F7/06

    Abstract: A method for performing a matrix multiplication operation is provided. The method includes: obtaining a matrix B1, a matrix A2, and an index matrix, wherein the index matrix comprises indexes, in a matrix A1, of elements in the matrix A2; generating m matrices B2 based on the index matrix and the matrix B1, wherein the m matrices B2 are all matrices with t rows and n columns, and each row of each matrix B2 is a row indicated in the matrix B1 by a corresponding element in the index matrix; and generating a matrix C based on the matrix A2 and the m matrices B2, wherein the matrix C is a product of the matrix A1 and the matrix B1.

    Method, circuit, and SOC for performing matrix multiplication operation

    公开(公告)号:US11263292B2

    公开(公告)日:2022-03-01

    申请号:US17324533

    申请日:2021-05-19

    Abstract: A method for performing a matrix multiplication operation is provided. The method includes: obtaining a matrix B1, a matrix A2, and an index matrix, wherein the index matrix comprises indexes, in a matrix A1, of elements in the matrix A2; generating m matrices B2 based on the index matrix and the matrix B1, wherein the m matrices B2 are all matrices with t rows and n columns, and each row of each matrix B2 is a row indicated in the matrix B1 by a corresponding element in the index matrix; and generating a matrix C based on the matrix A2 and the m matrices B2, wherein the matrix C is a product of the matrix A1 and the matrix B1.

    Multiplication circuit, system on chip, and electronic device

    公开(公告)号:US11249721B2

    公开(公告)日:2022-02-15

    申请号:US16822720

    申请日:2020-03-18

    Abstract: A multiplication circuit includes an addition subcircuit configured to obtain logarithmic field data a and b that correspond to A and B, and perform an addition operation on a and b to obtain c, where c includes an integral part and a fractional part, an exponentiation operation subcircuit configured to perform an exponentiation operation in which a base is 2 and an exponent is the fractional part of c, to obtain an exponentiation operation result, a shift subcircuit configured to shift the exponentiation operation result based on the integral part of c to obtain a shift result, and an output subcircuit configured to output a product of A and B based on signs of a and b and with reference to the shift result.

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