公开(公告)号：US20220206757A1

公开(公告)日：2022-06-30

申请号：US17698068

申请日：2022-03-18

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Chun Hang LEE ,  Zhenjiang DONG

IPC: G06F7/544

Abstract: A multiplier (500) configured to simultaneously implement a plurality of low bit width multiplication operations is provided. The multiplier (500) includes a multiplicator input end (550) for receiving two low bit width multiplicators, a multiplicand input end (560) for receiving two low bit width multiplicands, a mask circuit (540) for masking each low bit width multiplicator, and a multiplication operation circuit (502) for multiplying a mask result and a multiplicand. When a sum of bit widths of the multiplicators is smaller than the multiplicator input end (550) and a sum of bit widths of the multiplicands is smaller than the multiplicand input end (560), masking is performed on each of the low bit width multiplicators, so that the multiplier (500) may respectively implement two low bit width multiplication operations, which resolves a waste of hardware resources that occurs because the multiplier can only process multiplication operations in one data format.