公开(公告)号：US11573898B2

公开(公告)日：2023-02-07

申请号：US16995411

申请日：2020-08-17

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Randy Passint ,  Paul Frank ,  Russell L. Nicol ,  Thomas McGee ,  Michael Woodacre

IPC: G06F12/0831 ,  G06F13/40

Abstract: A node controller is provided to include a first interface to interface with one or more processors, a second interface including a plurality of ports to interface with node controllers within a base node and other nodes in the cache-coherent interconnect network. The node controller can further include a third interface to interface with a first plurality of memory devices and a cache coherence management logic. The cache coherence management logic can maintain, based on a first circuitry, hardware-managed cache coherency in the cache-coherent interconnect network. The cache coherence management logic can further facilitate, based on a second circuitry, software-managed cache coherency in the cache-coherent interconnect network.