公开(公告)号：US20120216156A1

公开(公告)日：2012-08-23

申请号：US13505286

申请日：2010-10-26

申请人： Hua-Yu Liu ,  Luoqi Chen ,  Hong Chen ,  Zhi-Pan Li ,  Jun Ye ,  Min-Chun Tsai ,  Youping Zhang ,  Yen-Wen Lu ,  Jiangwei Li

发明人： Hua-Yu Liu ,  Luoqi Chen ,  Hong Chen ,  Zhi-Pan Li ,  Jun Ye ,  Min-Chun Tsai ,  Youping Zhang ,  Yen-Wen Lu ,  Jiangwei Li

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/144 ,  G03F1/36 ,  G03F7/70125 ,  G03F7/70425 ,  G03F7/70441 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/50 ,  G06F17/5009

摘要： The present invention relates to a method of selecting a subset of patterns from a design, to a method of performing source and mask optimization, and to a computer program product for performing the method of selecting a subset of patterns from a design. According to certain aspects, the present invention enables coverage of the full design while lowering the computation cost by intelligently selecting a subset of patterns from a design in which the design or a modification of the design is configured to be imaged onto a substrate via a lithographic process. The method of selecting the subset of patterns from a design includes identifying a set of patterns from the design related to the predefined representation of the design. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes a similar predefined representation of the design as the set of patterns.

摘要翻译： 本发明涉及从设计中选择模式子集的方法，以及执行源和掩码优化的方法以及用于执行从设计中选择模式子集的方法的计算机程序产品。 根据某些方面，本发明能够覆盖整个设计，同时降低计算成本，通过智能地从设计中选择图案子集，其中设计的设计或修改被配置为经由光刻成像到衬底上 处理。 从设计中选择图案子集的方法包括从与设计的预定义表示相关的设计中识别一组图案。 通过根据该方法选择模式子集，所选择的模式子集构成与模式集合相似的设计表示。

公开(公告)号：US08739082B2

公开(公告)日：2014-05-27

申请号：US13505286

申请日：2010-10-26

申请人： Hua-Yu Liu ,  Luoqi Chen ,  Hong Chen ,  Zhi-Pan Li ,  Jun Ye ,  Min-Chun Tsai ,  Youping Zhang ,  Yen-Wen Lu ,  Jiangwei Li

发明人： Hua-Yu Liu ,  Luoqi Chen ,  Hong Chen ,  Zhi-Pan Li ,  Jun Ye ,  Min-Chun Tsai ,  Youping Zhang ,  Yen-Wen Lu ,  Jiangwei Li

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/144 ,  G03F1/36 ,  G03F7/70125 ,  G03F7/70425 ,  G03F7/70441 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/50 ,  G06F17/5009

摘要： The present invention relates to a method of selecting a subset of patterns from a design, to a method of performing source and mask optimization, and to a computer program product for performing the method of selecting a subset of patterns from a design. According to certain aspects, the present invention enables coverage of the full design while lowering the computation cost by intelligently selecting a subset of patterns from a design in which the design or a modification of the design is configured to be imaged onto a substrate via a lithographic process. The method of selecting the subset of patterns from a design includes identifying a set of patterns from the design related to the predefined representation of the design. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes a similar predefined representation of the design as the set of patterns.

摘要翻译： 本发明涉及从设计中选择模式子集的方法，以及执行源和掩码优化的方法以及用于执行从设计中选择模式子集的方法的计算机程序产品。 根据某些方面，本发明能够覆盖整个设计，同时降低计算成本，通过智能地从设计中选择图案子集，其中设计的设计或修改被配置为经由光刻成像到衬底上 处理。 从设计中选择图案子集的方法包括从与设计的预定义表示相关的设计中识别一组图案。 通过根据该方法选择模式子集，所选择的模式子集构成与模式集合相似的设计表示。

公开(公告)号：US08543947B2

公开(公告)日：2013-09-24

申请号：US12914954

申请日：2010-10-28

申请人： Hua-Yu Liu ,  Luoqi Chen ,  Hong Chen ,  Zhi-Pan Li

发明人： Hua-Yu Liu ,  Luoqi Chen ,  Hong Chen ,  Zhi-Pan Li

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/144 ,  G03F1/36 ,  G03F7/70125 ,  G03F7/70425 ,  G03F7/70441 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/50 ,  G06F17/5009

摘要： The present invention relates generally to selecting optimum patterns based on diffraction signature analysis, and more particularly to, using the optimum patterns for mask-optimization for lithographic imaging. A respective diffraction map is generated for each of a plurality of target patterns from an initial larger set of target patterns from the design layout. Diffraction signatures are identified from the various diffraction maps. The plurality of target patterns is grouped into various diffraction-signature groups, the target patterns in a specific diffraction-signature group having similar diffraction signature. A subset of target patterns is selected to cover all possible diffraction-signature groups, such that the subset of target patterns represents at least a part of the design layout for the lithographic process. The grouping of the plurality of target patterns may be governed by predefined rules based on similarity of diffraction signature. The predefined rules comprise coverage relationships existing between the various diffraction-signature groups.

摘要翻译： 本发明一般涉及基于衍射特征分析来选择最佳图案，并且更具体地涉及使用用于光刻成像的掩模优化的最佳图案。 从来自设计布局的初始较大的目标图案集合中的多个目标图案中的每一个生成相应的衍射图。 从各种衍射图识别衍射特征。 多个目标图案被分组成各种衍射签名组，具有相似衍射特征的特定衍射签名组中的目标图案。 选择目标图案的子集以覆盖所有可能的衍射签名组，使得目标图案的子集代表光刻工艺的设计布局的至少一部分。 多个目标图案的分组可以通过基于衍射签名的相似性的预定规则来管理。 预定义的规则包括存在于各种衍射签名组之间的覆盖关系。

公开(公告)号：US20110107280A1

公开(公告)日：2011-05-05

申请号：US12914954

申请日：2010-10-28

申请人： Hua-Yu Liu ,  Luoqi Chen ,  Hong Chen ,  Zhi-Pan Li

发明人： Hua-Yu Liu ,  Luoqi Chen ,  Hong Chen ,  Zhi-Pan Li

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/144 ,  G03F1/36 ,  G03F7/70125 ,  G03F7/70425 ,  G03F7/70441 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/50 ,  G06F17/5009

摘要： The present invention relates generally to selecting optimum patterns based on diffraction signature analysis, and more particularly to, using the optimum patterns for mask-optimization for lithographic imaging. A respective diffraction map is generated for each of a plurality of target patterns from an initial larger set of target patterns from the design layout. Diffraction signatures are identified from the various diffraction maps. The plurality of target patterns is grouped into various diffraction-signature groups, the target patterns in a specific diffraction-signature group having similar diffraction signature. A subset of target patterns is selected to cover all possible diffraction-signature groups, such that the subset of target patterns represents at least a part of the design layout for the lithographic process. The grouping of the plurality of target patterns may be governed by predefined rules based on similarity of diffraction signature. The predefined rules comprise coverage relationships existing between the various diffraction-signature groups.

摘要翻译： 本发明一般涉及基于衍射特征分析来选择最佳图案，更具体地说，涉及使用用于光刻成像的掩模优化的最佳图案。 从来自设计布局的初始较大的目标图案集合中的多个目标图案中的每一个生成相应的衍射图。 从各种衍射图识别衍射特征。 多个目标图案被分组成各种衍射签名组，具有相似衍射特征的特定衍射签名组中的目标图案。 选择目标图案的子集以覆盖所有可能的衍射签名组，使得目标图案的子集代表光刻工艺的设计布局的至少一部分。 多个目标图案的分组可以通过基于衍射签名的相似性的预定规则来管理。 预定义的规则包括存在于各种衍射签名组之间的覆盖关系。

公开(公告)号：US08887104B2

公开(公告)日：2014-11-11

申请号：US13823685

申请日：2011-09-01

申请人： Hua-Yu Liu ,  Jiangwei Li ,  Luoqi Chen ,  Wei Liu ,  Jiong Jiang

发明人： Hua-Yu Liu ,  Jiangwei Li ,  Luoqi Chen ,  Wei Liu ,  Jiong Jiang

IPC分类号： G06F17/50 ,  G03F7/20

CPC分类号： G06F17/5045 ,  G03F7/705 ,  G03F7/70941 ,  G06F17/5009

摘要： A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. Some of the system-specific effects included in the simulation are: a flare effect due to reflection from black border of a mask, a flare effect due to reflection from one or more reticle-masking blades defining an exposure slit, a flare effect due to overscan, a flare effect due reflections from a gas-lock sub-aperture of a dynamic gas lock (DGL) mechanism, and a flare effect due to contribution from neighboring exposure fields.

摘要翻译： 描述了一种用于降低由用于将设计布局成像到基板上的光刻设备产生的火炬的影响的方法。 通过将曝光场上的设计布局的密度图与点扩散函数（PSF）进行数学组合来模拟光刻设备的曝光区域中的耀斑图，其中可以在闪光图中对系统特定的影响 模拟。 通过使用确定的耀斑图计算设计布局的位置相关的光斑校正，从而减少了耀斑的影响。 仿真中包括的一些系统特定效果是：由于掩模的黑色边缘的反射引起的耀斑效应，由于限定曝光狭缝的一个或多个掩模版掩模片的反射引起的耀斑效应，由于 过扫描，来自动态气体锁（DGL）机构的气体锁定子孔的反射引起的闪光效应，以及由于来自相邻曝光场的贡献而产生的耀斑效果。

公开(公告)号：US20130185681A1

公开(公告)日：2013-07-18

申请号：US13823685

申请日：2011-09-01

申请人： Hua-Yu Liu ,  Jiangwei Li ,  Luoqi Chen ,  Wei Liu ,  Jiong Jiang

发明人： Hua-Yu Liu ,  Jiangwei Li ,  Luoqi Chen ,  Wei Liu ,  Jiong Jiang

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G03F7/705 ,  G03F7/70941 ,  G06F17/5009

摘要： A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. Some of the system-specific effects included in the simulation are: a flare effect due to reflection from black border of a mask, a flare effect due to reflection from one or more reticle-masking blades defining an exposure slit, a flare effect due to overscan, a flare effect due reflections from a gas-lock sub-aperture of a dynamic gas lock (DGL) mechanism, and a flare effect due to contribution from neighboring exposure fields.

摘要翻译： 描述了一种用于降低由用于将设计布局成像到基板上的光刻设备产生的火炬的影响的方法。 通过将曝光场上的设计布局的密度图与点扩散函数（PSF）进行数学组合来模拟光刻设备的曝光区域中的耀斑图，其中可以在闪光图中对系统特定的影响 模拟。 通过使用确定的耀斑图计算设计布局的位置相关的光斑校正，从而减少了耀斑的影响。 仿真中包括的一些系统特定效果是：由于掩模的黑色边缘的反射引起的耀斑效应，由于限定曝光狭缝的一个或多个掩模版掩模片的反射引起的耀斑效应，由于 过扫描，来自动态气体锁（DGL）机构的气体锁定子孔的反射引起的闪光效应，以及由于来自相邻曝光场的贡献而产生的耀斑效果。

公开(公告)号：US07117478B2

公开(公告)日：2006-10-03

申请号：US11037988

申请日：2005-01-18

申请人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

发明人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

IPC分类号： G06F17/50 ,  G03F1/00 ,  G21K5/00 ,  G06F19/00

CPC分类号： G06F17/5009 ,  G03F1/00 ,  G03F7/004 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G06T7/0004 ,  G06T2207/30148 ,  G21K5/00

摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

公开(公告)号：US20050122500A1

公开(公告)日：2005-06-09

申请号：US11037988

申请日：2005-01-18

申请人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

发明人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

IPC分类号： G03B27/54 ,  G03F20060101 ,  G03F7/20 ,  G06F17/50 ,  G06K9/00 ,  G06T7/00

CPC分类号： G06F17/5009 ,  G03F1/00 ,  G03F7/004 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G06T7/0004 ,  G06T2207/30148 ,  G21K5/00

摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

公开(公告)号：US20050097500A1

公开(公告)日：2005-05-05

申请号：US10981914

申请日：2004-11-04

申请人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

发明人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

IPC分类号： G03B27/54 ,  G03F20060101 ,  G03F7/20 ,  G06F17/50 ,  G06K9/00 ,  G06T7/00

CPC分类号： G06F17/5009 ,  G03F1/00 ,  G03F7/004 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G06T7/0004 ,  G06T2207/30148 ,  G21K5/00

摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

公开(公告)号：US07111277B2

公开(公告)日：2006-09-19

申请号：US10981914

申请日：2004-11-04

申请人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

发明人： Jun Ye ,  Yen-Wen Lu ,  Yu Cao ,  Luoqi Chen ,  Xun Chen

IPC分类号： G06F17/50 ,  G03F1/00 ,  G21K5/00 ,  G06F19/00

CPC分类号： G06F17/5009 ,  G03F1/00 ,  G03F7/004 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G06T7/0004 ,  G06T2207/30148 ,  G21K5/00

摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.