公开(公告)号：US11843459B2

公开(公告)日：2023-12-12

申请号：US17837916

申请日：2022-06-10

Applicant: Huawei Technologies Co., Ltd.

Inventor： Vladimir Vitalievich Gritsenko ,  Vladislav Nikolaevich Obolentsev ,  Dmitrii Yurievich Bukhan ,  Aleksei Eduardovich Maevskii ,  Hongchen Yu ,  Kun Gu ,  Jie Chen ,  Shiyao Xiao ,  Man Zhao ,  Jun Chen ,  Yunlong Li

IPC: H04L1/00

CPC classification number: H04L1/0041 ,  H04L1/0045 ,  H04L1/0071

Abstract: The present disclosure provides an encoding and decoding device implementing an improved forward error correction (FEC) coding/decoding method. In particular, the encoding device is configured to encode a stream of data symbols using a spatially coupled code (e.g. staircase codes, braided block codes or continuously interleaved block codes), wherein at least one generalized error location (GEL) code is used as a component code of the spatially coupled code. Accordingly, the decoding device is configured to decode a sequence of encoded symbol blocks using a spatially coupled code, wherein at least one GEL code is used as a component code of the spatially coupled code. Thereby, a suitable spatially coupled FEC code that allows for very low-latency, high-throughput, high-rate applications with a low-complexity decoding procedure, and allows for mitigation of the error-floor, is designed.

公开(公告)号：US12224767B2

公开(公告)日：2025-02-11

申请号：US18167380

申请日：2023-02-10

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Artem Vitalyevich Cherenkov ,  Man Zhao ,  Mikhail Alexandrovich Linnik ,  Yijie Wang

IPC: H03M1/66 ,  H03M1/06 ,  H03M1/08

Abstract: A signal processing apparatus includes a plurality of time-interleaving digital-to-analog converters each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal. The signal processing apparatus includes analog multiplexer that samples the plurality of sub-DAC output signals at a preset multiplexer clock frequency and generates a multiplexer output signal. The signal processing apparatus further includes a local ADC that receives the multiplexer output signal and generate a digital feedback signal. The signal processing apparatus further includes a digital compensation engine that receives the digital feedback signal from the local ADC and determine one or more distortion compensation parameters. The signal processing apparatus further includes a digital pre-processing stage that receives the one or more distortion compensation parameters from the digital compensation engine and performs distortion compensation pre-processing on the digital input signal.