公开(公告)号：US20210043245A1

公开(公告)日：2021-02-11

申请号：US17080242

申请日：2020-10-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Bingwu Ji ,  Tanfu Zhao ,  Yunming Zhou ,  Min Fan ,  Zhiyan Li ,  Yunpeng Wang

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4074 ,  G11C7/10

Abstract: A memory and a signal processing method are provided. The memory includes a latch circuit, a decoding circuit, a storage array, a read circuit, and a write circuit. The storage array includes M rows and N columns of bitcells. The latch circuit is configured to receive a first address and a second address. The decoding circuit is configured to: determine a first bitcell based on the first address, and determine a second bitcell based on the second address. The write circuit is configured to: receive data, and write the data into the first bitcell through a first port of the first bitcell. The read circuit is configured to read, through the first port of the first bitcell, data stored in the first bitcell; and is further configured to read, through a second port of the second bitcell, data stored in the second bitcell. Implementing this application can implement 1R1RW.

公开(公告)号：US11276458B2

公开(公告)日：2022-03-15

申请号：US17080242

申请日：2020-10-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Bingwu Ji ,  Tanfu Zhao ,  Yunming Zhou ,  Min Fan ,  Zhiyan Li ,  Yunpeng Wang

IPC: G11C8/00 ,  G11C11/4091 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094

Abstract: A memory and a signal processing method are provided. The memory includes a latch circuit, a decoding circuit, a storage array, a read circuit, and a write circuit. The storage array includes M rows and N columns of bitcells. The latch circuit is configured to receive a first address and a second address. The decoding circuit is configured to: determine a first bitcell based on the first address, and determine a second bitcell based on the second address. The write circuit is configured to: receive data, and write the data into the first bitcell through a first port of the first bitcell. The read circuit is configured to read, through the first port of the first bitcell, data stored in the first bitcell; and is further configured to read, through a second port of the second bitcell, data stored in the second bitcell. Implementing this application can implement 1R1RW.