公开(公告)号：US20080144414A1

公开(公告)日：2008-06-19

申请号：US12021762

申请日：2008-01-29

申请人： Hyun Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type is configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.

摘要翻译： 感测放大器包括一对感测位线和第一和第二MOS读出放大器。 第一MOS读出放大器在其中具有第一导电类型的第一对MOS晶体管，其电耦合在该对感测位线之间。 该电耦合被提供为使得第一对MOS晶体管中的每一个具有电连接到该对感测位线中的相应一个和第一对MOS晶体管的第二源极/漏极端子的第一源极/漏极端子 电连接在一起。 第一导电类型的第一对MOS晶体管被配置为具有不同的阈值电压或支持不同的阈值电压偏置。 第二MOS读出放大器具有第一对第二导电类型的MOS晶体管，它们在一对感测位线之间电耦合。

公开(公告)号：US07710807B2

公开(公告)日：2010-05-04

申请号：US12021762

申请日：2008-01-29

申请人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type is configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.

摘要翻译： 感测放大器包括一对感测位线和第一和第二MOS读出放大器。 第一MOS读出放大器在其中具有第一导电类型的第一对MOS晶体管，其电耦合在该对感测位线之间。 该电耦合被提供为使得第一对MOS晶体管中的每一个具有电连接到该对感测位线中的相应一个和第一对MOS晶体管的第二源极/漏极端子的第一源极/漏极端子 电连接在一起。 第一导电类型的第一对MOS晶体管被配置为具有不同的阈值电压或支持不同的阈值电压偏置。 第二MOS读出放大器具有第一对第二导电类型的MOS晶体管，它们在一对感测位线之间电耦合。

公开(公告)号：US07345939B2

公开(公告)日：2008-03-18

申请号：US11185351

申请日：2005-07-20

申请人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type are configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.

摘要翻译： 感测放大器包括一对感测位线和第一和第二MOS读出放大器。 第一MOS读出放大器在其中具有第一导电类型的第一对MOS晶体管，其电耦合在该对感测位线之间。 该电耦合被提供为使得第一对MOS晶体管中的每一个具有电连接到该对感测位线中的相应一个和第一对MOS晶体管的第二源极/漏极端子的第一源极/漏极端子 电连接在一起。 第一导电类型的第一对MOS晶体管被配置为具有不同的阈值电压或支持不同的阈值电压偏置。 第二MOS读出放大器具有第一对第二导电类型的MOS晶体管，它们在一对感测位线之间电耦合。

公开(公告)号：US20060023537A1

公开(公告)日：2006-02-02

申请号：US11185351

申请日：2005-07-20

申请人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A semiconductor memory device and a bit line sensing method thereof are disclosed. The semiconductor memory device includes a first memory cell connected between a first word line accessed by a first address and an inverted bit line; a second memory cell connected between a second word line accessed by a second address and a bit line; a first type sense amplifier serially connected between the bit line and the inverted bit line and having a first type first MOS transistor sensing the inverted bit line and a first type second MOS transistor sensing the bit line if a first enable signal of a first voltage is applied; a second type first sense amplifier serially connected between the bit line and the inverted bit line and having a second type first MOS transistor sensing the inverted bit line and a second type second MOS transistor sensing the bit line if a second enable signal of a second voltage is applied, wherein the second type first MOS transistor has a better sensing ability than the second type second MOS transistor; and a second type second sense amplifier serially connected between the bit line and the inverted bit line and having a second type third MOS transistor sensing the inverted bit line and a second type fourth MOS transistor sensing the bit line if a third enable signal of the second voltage is applied, wherein the second type fourth MOS transistor has a better sensing ability than the second type third MOS transistor.

摘要翻译： 公开了一种半导体存储器件及其位线检测方法。 半导体存储器件包括连接在由第一地址和反向位线访问的第一字线之间的第一存储器单元; 连接在由第二地址访问的第二字线和位线之间的第二存储器单元; 第一类型读出放大器串联连接在位线和反相位线之间，并且具有感测反向位线的第一类型第一MOS晶体管和感测位线的第一类型第二MOS晶体管，如果第一电压的第一使能信号为 应用; 串联连接在位线和反相位线之间的第二类型的第一读出放大器，并且具有检测反相位线的第二类型的第一MOS晶体管和感测位线的第二类型的第二MOS晶体管，如果第二电压的第二使能信号 其中所述第二类型的第一MOS晶体管具有比所述第二类型的第二MOS晶体管更好的感测能力; 以及第二类型的第二读出放大器，其串联连接在位线和反相位线之间，并且具有感测反转位线的第二类型的第三MOS晶体管和感测位线的第二类型的第四MOS晶体管，如果第二个 施加电压，其中第二类型的第四MOS晶体管具有比第二类型的第三MOS晶体管更好的感测能力。

公开(公告)号：US20060056218A1

公开(公告)日：2006-03-16

申请号：US11221684

申请日：2005-09-08

申请人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

发明人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C8/14

摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.

摘要翻译： 半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。 存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。 位线读出放大器可以被配置为感测和放大位线对的数据。 子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。 此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。 电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。 局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。 列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。 字选择信号线和主字线可以沿着与子字线相同的方向布置在电极上方的第三层上。 还讨论了信号线布置的相关方法。

公开(公告)号：US06452828B1

公开(公告)日：2002-09-17

申请号：US09886202

申请日：2001-06-20

申请人： Sang-Seok Kang ,  Jong-Hyun Choi ,  Jong-Eon Lee

发明人： Sang-Seok Kang ,  Jong-Hyun Choi ,  Jong-Eon Lee

IPC分类号： G11C506

CPC分类号： G11C11/4085 ,  G11C8/08

摘要： Disclosed is a dynamic random access memory (DRAM) device having word line low voltage supply lines for driving word lines in a mesh structure. The DRAM device includes a plurality of cell arrays each of which is formed of memory cells coupled to word lines and bit lines in a matrix. The memory device further includes regions of sense amplifiers disposed between the cell arrays arranged along the row direction, regions of word line drivers disposed between the cell arrays arranged along the column direction, conjunction regions disposed at positions adjacent to the regions of the sense amplifiers and word line drivers, and a plurality of word line low voltage supply lines disposed on the conjunction regions. The word line low voltage supply lines are electrically interconnected for each other at least on the conjunction regions. According to the layout arrangement, loadings of the word line low voltage supply lines are almost equally distributed, and thereby word line low noise are decreased.

公开(公告)号：US07259978B2

公开(公告)日：2007-08-21

申请号：US11221684

申请日：2005-09-08

申请人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

发明人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C8/14

摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.

摘要翻译： 半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。 存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。 位线读出放大器可以被配置为感测和放大位线对的数据。 子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。 此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。 电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。 局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。 列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。 字选择信号线和主字线可以沿与子字线相同的方向布置在电极上方的第三层上。 还讨论了信号线布置的相关方法。

公开(公告)号：US06473325B2

公开(公告)日：2002-10-29

申请号：US09882209

申请日：2001-06-15

申请人： Yun-Sang Lee ,  Sang-Suk Kang ,  Jae-Hoon Joo ,  Jong-Eon Lee

发明人： Yun-Sang Lee ,  Sang-Suk Kang ,  Jae-Hoon Joo ,  Jong-Eon Lee

IPC分类号： G11C506

CPC分类号： G11C7/065 ,  G11C11/4074 ,  G11C11/4091

摘要： A layout of a bit line sensing control circuit for a semiconductor memory device includes two bit line pairs extending in a first direction. A power contact is arranged between the two bit line pairs. A power gate is arranged around the power contact. A plurality of sense transistors respectively have a plurality of sense transistor gates. The plurality of sense transistor gates are arranged around the power gate. A pair of control line contacts is arranged in a second direction at an adjacent location outside the two bit line pairs. A control line extends in the second direction and is connected to the power gate through the pair of control line contacts. A power line extends in the second direction adjacent to the control line and is connected to an active area surrounded by the power gate through the power contact.

摘要翻译： 半导体存储器件的位线检测控制电路的布局包括沿第一方向延伸的两个位线对。 电源触点设置在两个位线对之间。 电源端口设置在电源触点周围。 多个感测晶体管分别具有多个感测晶体管栅极。 多个感测晶体管栅极布置在功率门周围。 一对控制线触点在两个位线对之外的相邻位置处沿第二方向布置。 控制线在第二方向上延伸并且通过一对控制线触点连接到电源门。 电力线在与控制线相邻的第二方向上延伸，并且通过电力接触连接到被电力门围绕的有效区域。

公开(公告)号：US20050094448A1

公开(公告)日：2005-05-05

申请号：US10972119

申请日：2004-10-21

申请人： Jong-Eon Lee ,  Young-Hyun Jun

发明人： Jong-Eon Lee ,  Young-Hyun Jun

IPC分类号： G11C7/00 ,  G11C29/50

CPC分类号： G11C29/50012 ,  G11C29/50

摘要： An integrated circuit device disclosed herein includes a test device and a setup and hold measuring circuit. The setup and hold measuring circuit generates a reference signal and a data signal in response to an external clock signal in a test mode of operation. The test device receives the data signal in response to a reference signal, and outputs the inputted data signal as a setup and hold determining circuit. One of the reference signal and the data signal is a multiphase signal synchronized with the external clock signal. The setup and hold measuring circuit detects whether the output of the test device indicates a valid value of the data signal, and generates the detected result to the external as a setup/hold timing margin through at least one pad.

摘要翻译： 本文公开的集成电路装置包括测试装置和建立和保持测量电路。 建立和保持测量电路在测试操作模式下响应外部时钟信号产生参考信号和数据信号。 测试装置响应于参考信号接收数据信号，并输出输入的数据信号作为建立和保持确定电路。 参考信号和数据信号之一是与外部时钟信号同步的多相信号。 建立和保持测量电路检测测试装置的输出是否指示数据信号的有效值，并通过至少一个焊盘将检测结果作为建立/保持定时裕度产生到外部。

公开(公告)号：US07551513B2

公开(公告)日：2009-06-23

申请号：US11342161

申请日：2006-01-26

申请人： Hong-Goo Yoon ,  Jong-Eon Lee

发明人： Hong-Goo Yoon ,  Jong-Eon Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C8/14

摘要： A semiconductor memory device includes a sub word line driver for selectively connecting one of sub word lines with a main word line and applying a boosted voltage having a level higher than a power source voltage to a selected sub word line. The device includes a sub word line driver control signal generator. The sub word line driver control signal generator receives an isolation signal applied to electrically insulate a sense amplifier from a bit line connected to memory cells constituting a memory cell array of the device, and generates a driver control signal for determining whether the sub word line driver operates or not. Thereby, a load of sub word line driver control signal generator can be reduced and so power consumption is reduced.

摘要翻译： 半导体存储器件包括用于选择性地将子字线中的一条与主字线连接并且将具有高于电源电压的电平的升压电压施加到所选择的子字线的子字线驱动器。 该装置包括一个子字线驱动器控制信号发生器。 子字线驱动器控制信号发生器接收一个隔离信号，该隔离信号被施加以将读出放大器与构成该器件的存储单元阵列的存储单元连接的位线电绝缘，并产生用于确定子字线驱动器 经营与否 由此，能够减少副字线驱动控制信号发生器的负载，降低功耗。