公开(公告)号：US20190109646A1

公开(公告)日：2019-04-11

申请号：US16204909

申请日：2018-11-29

Applicant: INPHI CORPORATION

Inventor： Oscar Ernesto AGAZZI ,  Diego Ernesto CRIVELLI ,  Paul VOOIS ,  Ramiro Rogelio LOPEZ ,  Jorge Manuel FINOCHIETTO ,  Norman L. SWENSON ,  Mario Rafael HUEDA ,  Hugo Santiago CARRER ,  Vadim GUTNIK ,  Adrián Ulises MORALES ,  Martin Ignacio DEL BARCO ,  Martin Carlos ASINARI ,  Federico Nicolas PAREDES ,  Alfredo Javier TADDEI ,  Mauro Marcelo BRUNI ,  Damian Alfonso MORERO ,  Facundo Abel Alcides RAMOS ,  María Laura FERSTER ,  Elvio Adrian SERRANO ,  Pablo Gustavo QUIROGA ,  Roman Antonio ARENAS ,  Matias German SCHNIDRIG ,  Alejandro Javier SCHWOYKOSKI

IPC: H04B10/516 ,  H04B10/40 ,  H04L7/00 ,  H04B10/61

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

公开(公告)号：US20170317759A1

公开(公告)日：2017-11-02

申请号：US15647765

申请日：2017-07-12

Applicant: INPHI CORPORATION

Inventor： Oscar Ernesto AGAZZI ,  Diego Ernesto CRIVELLI ,  Paul VOOIS ,  Ramiro Rogelio LOPEZ ,  Jorge Manuel FINOCHIETTO ,  Norman L. SWENSON ,  Mario Rafael HUEDA ,  Hugo Santiago CARRER ,  Vadim GUTNIK ,  Adrián Ulises MORALES ,  Martin Ignacio DEL BARCO ,  Martin Carlos ASINARI ,  Federico Nicolas PAREDES ,  Alfredo Javier TADDEI ,  Mauro Marcelo BRUNI ,  Damian Alfonso MORERO ,  Facundo Abel Alcides RAMOS ,  María Laura FERSTER ,  Elvio Adrian SERRANO ,  Pablo Gustavo QUIROGA ,  Roman Antonio ARENAS ,  Matias German SCHNIDRIG ,  Alejandro Javier SCHWOYKOSKI

IPC: H04B10/516 ,  H04L7/00

CPC classification number: H04B10/516 ,  H04B10/40 ,  H04B10/61 ,  H04L7/0075

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

公开(公告)号：US20200044744A1

公开(公告)日：2020-02-06

申请号：US16600328

申请日：2019-10-11

Applicant: INPHI CORPORATION

Inventor： Oscar Ernesto AGAZZI ,  Diego Ernesto CRIVELLI ,  Paul VOOIS ,  Ramiro Rogelio LOPEZ ,  Jorge Manuel FINOCHIETTO ,  Norman L. SWENSON ,  Mario Rafael HUEDA ,  Hugo Santiago CARRER ,  Vadim GUTNIK ,  Adrián Ulises MORALES ,  Martin Ignacio DEL BARCO ,  Martin Carlos ASINARI ,  Federico Nicolas PAREDES ,  Alfredo Javier TADDEI ,  Mauro Marcelo BRUNI ,  Damian Alfonso MORERO ,  Facundo Abel Alcides RAMOS ,  María Laura FERSTER ,  Elvio Adrian SERRANO ,  Pablo Gustavo QUIROGA ,  Roman Antonio ARENAS ,  Matias German SCHNIDRIG ,  Alejandro Javier SCHWOYKOSKI

IPC: H04B10/516 ,  H04B10/40 ,  H04B10/61 ,  H04L7/00

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

公开(公告)号：US20180062760A1

公开(公告)日：2018-03-01

申请号：US15800745

申请日：2017-11-01

Applicant: INPHI CORPORATION

Inventor： Diego Ernesto CRIVELLI ,  Mario Rafael HUEDA ,  Hugo Santiago CARRER ,  Jeffrey ZACHAN ,  Vadim GUTNIK ,  Martin Ignacio DEL BARCO ,  Ramiro Rogelio LOPEZ ,  Shih Cheng WANG ,  Geoffrey O. HATCHER ,  Jorge Manuel FINOCHIETTO ,  Michael YEO ,  Andre CHARTRAND ,  Norman L. SWENSON ,  Paul VOOIS ,  Oscar Ernesto AGAZZI

IPC: H04B10/61 ,  H04B10/40 ,  H04B10/2569

CPC classification number: H04B10/6162 ,  H04B10/2569 ,  H04B10/40 ,  H04B10/6161

Abstract: A transceiver for fiber optic communications. The transceiver can include a transmitter module having a transmitter host interface configured to receive an input host signal; a transmitter framer configured to frame the input host signal and to generate a framed host signal; and a transmitter coder configured to encode the framed host signal to generate an encoded host signal for transmission over a communication channel. The transceiver can also include a receiver module having a bulk chromatic dispersion, fiber length estimation, and coarse carrier recovery circuit configured to equalize a digital input ingress signal to generate an equalized ingress signal; a receiver framer configured to frame the equalized ingress signal to generate a framed ingress signal; and a receiver host interface configured to output the framed ingress signal. The receiver host interface is compatible with a framing protocol of the receiver framer.