公开(公告)号：US20170329609A1

公开(公告)日：2017-11-16

申请号：US15528079

申请日：2014-12-17

Applicant: INTEL CORPORATION

Inventor： DMITRY SIVKOV ,  IGOR ERMOLAEV

IPC: G06F9/30

CPC classification number: G06F9/30065 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30076 ,  G06F9/30145

Abstract: An apparatus and method for performing a spin-loop jump. One embodiment of a processor comprises: jump-pause execution logic to execute a jump-pause instruction, the jump-pause instruction to specify a condition and identify a destination instruction; wherein responsive to the execution of the jump-pause instruction, the jump-pause execution logic is to provide a hint that a loop between the jump-pause instruction and the destination instruction comprises a spin-wait loop and to test the condition, the jump-pause execution logic to delay execution by a specified amount prior to jumping to the destination instruction if the condition is satisfied. A second embodiment of a processor comprises test-subtract execution logic to execute a test-subtract instruction, the test-subtract instruction to decrement the counter value in a second source register, the test-subtract execution logic to further test the monitored value in a first source register or memory and the counter value in the second source register, wherein the test-subtract execution logic is to exit a spin-wait loop if the monitored value has a value indicating an exit condition or if the counter value is equal to zero.