公开(公告)号：US20190095316A1

公开(公告)日：2019-03-28

申请号：US15714963

申请日：2017-09-25

Applicant: INTEL CORPORATION

Inventor： SHANKER RAMAN NAGESH ,  RAMAMURTHY KRITHIVAS ,  MANDIRA KUMAR SATHANANTHAM

IPC: G06F11/36 ,  G06F11/34 ,  H04L29/08

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive debug trace information via one or more pins, generate a packet comprising the debug trace information and a header, the header comprising header information to send the packet to a device coupled via one or more network connections, determine a location in a data buffer of an interface controller for the packet, and write the packet to the data buffer of the interface controller at the location.